Datasheet > IN74AC112N

IN74AC112N

更新时间： 2024-11-26 05:39:19

品牌	Logo	应用领域
IKSEMICON		触发器栅
页数	文件大小	规格书
6页	232K
描述
Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

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IN74AC112N 数据手册

TECHNICAL DATA

IN74AC112

Dual J-K Flip-Flop

with Set and Reset

High-Speed Silicon-Gate CMOS

The IN74AC112 is identical in pinout to the LS/ALS112,

HC/HCT112. The device inputs are compatible with standard CMOS

outputs; with pullup resistors, they are compatible with LS/ALS outputs.

Each flip-flop is negative-edge clocked and has active-low

asynchronous Set and Reset inputs.

•

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2.0 to 6.0 V

Low Input Current: 1.0 μA; 0.1 μA @ 25°C

High Noise Immunity Characteristic of CMOS Devices

Outputs Source/Sink 24 mA

ORDERING INFORMATION

IN74AC112N Plastic

IN74AC112D SOIC

T_A= -40° to 85° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs

Clock

Outputs

Set

Reset

L^*

No Change

Toggle

No Change

* Both outputs will remain low as long as Set and Reset are

low, but the output states are unpredictable if Set and Reset

go high simultaneously

PIN 16=V_CC

PIN 8 = GND

X = Don’t Care

Rev. 00

12 3 4 5 6

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