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IMISG543CYB PDF预览

IMISG543CYB

更新时间： 2024-01-24 08:36:13
品牌 Logo 应用领域
其他 - ETC 时钟发生器
页数 文件大小 规格书
15页 213K
描述
CPU System Clock Generator

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IMISG543CYB 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP-48针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.88
Is Samacsys：N其他特性：ALSO AVAILABLE FO= 16MHZ AS PER CRYSTAL AND REF OSC
JESD-30 代码：R-PDSO-G48JESD-609代码：e0
长度：15.88 mm湿度敏感等级：1
端子数量：48最高工作温度：70 °C
最低工作温度：最大输出时钟频率：83.52 MHz
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP48,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：220
电源：2.5,3.3 V主时钟/晶体标称频率：14.318 MHz
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：Clock Generators最大压摆率：220 mA
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.64 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.49 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

IMISG543CYB 数据手册

 浏览型号IMISG543CYB的Datasheet PDF文件第1页浏览型号IMISG543CYB的Datasheet PDF文件第3页浏览型号IMISG543CYB的Datasheet PDF文件第4页浏览型号IMISG543CYB的Datasheet PDF文件第5页浏览型号IMISG543CYB的Datasheet PDF文件第6页浏览型号IMISG543CYB的Datasheet PDF文件第7页 
SG543  
I2C Clock Generator for 3 DIMM, Pentium , Pentium II & Pro Boards.  
Approved Product  
PIN DESCRIPTION  
Pin Number  
Pin Name  
Xin  
PWR  
VDD  
I/O  
I
Description  
These pins form an on-chip reference oscillator when connected to  
terminals of an external parallel resonant crystal (nominally 14.318  
MHz). Xin may also serve as input for an externally generated reference  
signal. If the external input is used, Pin 5 is left unconnected.  
4
5
7
VDD  
VDDP  
O
O
Xout  
PCI_F  
This is a bi-directional pin. During power up, this pin is an input for  
frequency selection S1 control bit (see page 1, and app note on page  
12) and sets the bit to its initial state. After a fixed period of time (see  
fig.1, page 3), this pin becomes a low skew PCI clock output that does  
not stop when PS# (pin 15 or I2C register bit) is asserted.  
VDD  
I
*
S1  
This is a bi-directional pin. During power up, this pin is an input for  
frequency selection S2 control bit (see page1,and app note on page 12)  
and sets the bit to its initial state. After a fixed period of time (see fig.1,  
VDDP  
O
PCI0  
8
page 3), this pin becomes a low skew PCI clock output that stops when  
PS# (pin 15 or its I2C register bit) is asserted.  
VDD  
I
*
S2  
Low skew (<250 pS) clock outputs for PCI frequencies.  
10, 11, 12, 13  
15  
VDDP  
VDDP  
O
O
PCI (1:4)  
PCI5  
IF MODE=1 this pin becomes low skew (<250 pS) clock outputs for PCI  
frequencies.  
If MODE=0 then this pin controls whether the PCI clock outputs (except  
for PCI-F) are enabled (set to a logic 1) or disabled (set to a logic 0)  
VDD  
I
*
PS#  
Low skew (<250 pS) clock outputs for host frequencies such as CPU,  
AGP, Chipset, Cache.  
44, 43, 41, 40  
VDDC  
O
CPU(0:3)  
Synchronous DRAM DIM clocks.  
38, 37, 35, 34, 32, 31,  
29, 28, 21, 20, 18, 17  
47  
VDDSD(0:2)  
O
SDRAM(0:11)  
Buffered clock of the crystal oscillator (nominally 14.31818 MHz).  
VDDI  
VDD  
O
O
IOAPIC  
REF1  
IF MODE=1 this pin becomes a buffered copy of the internal crystal  
oscillator (nominally 14.31818 MHz)  
46  
If MODE=0 then this pin controls whether the CPU clock outputs are  
enabled (set to a logic 1) or disabled (set to a logic 0).  
VDD  
I
*
CS#  
This pin is a Buffered output of the crystal reference frequency.  
2
VDD  
VDD  
O
I/O  
REF0  
48 MHz  
This is a bi-directional pin. During power up, this pin is an input for  
frequency selection S0 control bit (see page1,and app note  
26  
on page 12) and sets the bit to its initial state. After a fixed period of  
time (see fig.1, page 3), this pin becomes a 48 MHz frequency clock.  
VDD  
VDD  
I
*
O
S0  
This is a bi-directional pin. During power up, this pin is an input that  
enables (0) or disables (1) the power management shared pins (46 and  
15) (see app note on page 12) and sets the bit to its initial state. After a  
fixed period of time (see fig.1, page 3), this pin becomes a 24 MHz  
frequency clock.  
24 MHz  
25  
VDD  
I
MODE  
*
*A 10K ohm resistor to VDD or VSS is required to insure that the device’s internal storage registers are correctly set at  
power up.  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571  
Rev.1.7  
8/14/98  
Page 2 of 15  
1234567...15

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