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IMISG543CYB PDF预览

IMISG543CYB

更新时间: 2024-02-07 23:28:19
品牌 Logo 应用领域
其他 - ETC 时钟发生器
页数 文件大小 规格书
15页 213K
描述
CPU System Clock Generator

IMISG543CYB 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP-48针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.88
Is Samacsys:N其他特性:ALSO AVAILABLE FO= 16MHZ AS PER CRYSTAL AND REF OSC
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:15.88 mm湿度敏感等级:1
端子数量:48最高工作温度:70 °C
最低工作温度:最大输出时钟频率:83.52 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):220
电源:2.5,3.3 V主时钟/晶体标称频率:14.318 MHz
认证状态:Not Qualified座面最大高度:2.79 mm
子类别:Clock Generators最大压摆率:220 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.64 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.49 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

IMISG543CYB 数据手册

 浏览型号IMISG543CYB的Datasheet PDF文件第1页浏览型号IMISG543CYB的Datasheet PDF文件第2页浏览型号IMISG543CYB的Datasheet PDF文件第3页浏览型号IMISG543CYB的Datasheet PDF文件第5页浏览型号IMISG543CYB的Datasheet PDF文件第6页浏览型号IMISG543CYB的Datasheet PDF文件第7页 
SG543  
I2C Clock Generator for 3 DIMM, Pentium , Pentium II & Pro Boards.  
Approved Product  
POWER MANAGEMENT FUNCTIONS  
When MODE=0, pins 15 and 46 are inputs PS# (PCI_STOP#), and CS# (CPU_STOP#), respectively (when MODE=1,  
these functions are not available). A particular output is enabled only when both the serial interface and these pins  
indicate that it should be enabled. The IMISG543 clocks may be disabled according to the following table in order to  
reduce power consumption. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions  
from running to stopped. The CPU/AGP and PCI clocks transition between running and stopped by waiting for one  
positive edge on PCICLK_F followed by a negative edge on the clock of interest, after which high levels of the output are  
either enabled or disabled.  
CPU_STOP#  
PCI_STOP#  
CPU  
LOW  
PCI  
LOW  
OTHER CLKs  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
XTAL & VCOs  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
0
0
1
1
0
1
0
1
LOW  
RUNNING  
LOW  
RUNNING  
RUNNING  
RUNNING  
Please note that all clocks can be individually asynchronously enabled or stopped via the 2-wire I2C control interface. In  
this case all clocks are stopped in the low state.  
POWER MANAGEMENT TIMING  
PCICLK_F  
PCI_STOP#  
PCICLK(0:5)  
CPU_STOP#  
CPUCLK(0:3)  
Fig. 2  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571  
Rev.1.7  
8/14/98  
Page 4 of 15  

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