Datasheet > IMISC674BYB

IMISC674BYB

更新时间： 2024-11-10 23:58:39

品牌	Logo	应用领域
其他 - ETC		时钟发生器
页数	文件大小	规格书
11页	141K
描述
CPU System Clock Generator

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中文翻译

获取价格

数据手册

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IMISC674BYB 数据手册

SC674

I²C Clock Generator for Pentium and Pentium II with 440LX

Chipset and 4 DIMMs

Approved Product

PRODUCT FEATURES

FREQUENCY TABLE

SEL

CPU

60.0

66.6

PCI

30.0

33.3

Supports Pentium^ä& Pentium^äII using the

440LX chipset..

5 CPU / AGP clocks

Up to 16 SDRAM clocks for 4 DIMMs.

7 PCI synchronous clocks.

Optional common or mixed supply mode:

(VDD = VDDP = VDDC = 3.3V) or

(VDD = VDDP = 3.3V, VDDC = 2.5V)

Supports Power Management

< 250ps skew CPU and SDRAM clocks.

< 250ps skew among PCI clocks.

I²C 2-Wire serial interface

Programmable registers featuring:

- enable/disable each output pin

- mode as tri-state, test, or normal

3 IOAPIC clocks for multiprocessor support.

56-pin SSOP package

CONNECTION DIAGRAM

VDD

IOAPIC3

VDDC

IOAPIC1

IOAPIC2

VSS

CPUCLK1

CPUCLK2

VDDC

CPUCLK3

CPUCLK4

VSS

CPUCLK5

SDRAM1

SDRAM2

VDDP

SDRAM3

SDRAM4

VSS

SDRAM5

SDRAM6/ PD#

VDDP

SDRAM7 / CS#

SDRAM8 / PS#

VSS

SDRAM13

SDRAM14

VSS

REF

VSS

XIN

XOUT

VDDP

PCICLK_F

PCICLK1

VSS

PCICLK2

PCICLK3

PCICLK4

PCICLK5

VDDP

PCICLK6

VSS

SDRAM12

SDRAM11

VDDP

SDRAM10

SDRAM9

VSS

SDRAM16

SDRAM15

VDDP

BLOCK DIAGRAM

XIN

REF

XOUT

IOAPIC(1:3)

VDDC

CPUCLK(1:5)

Sel

PLL

Clock

Gen.

PCICLK(1:6)

PCICLK_F

dly

Sdata

Sclock

PS#

CS#

PD#

SDRAM(1:5, 9:16)

SDRAM(1:16)

SDATA

SDCLK

Sel

Mode

PS# : PCI_STOP#

CS# : CPU_STOP#

PD# : PWR_DWN#

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571

Rev. 1.7

4/23/97

Page 1 of 11

12 3 4 5 6 7...11

中文翻译

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