IMI145152
FREQUENCY SYNTHESIZER
CMOS LSI
February 1996
PARALLEL TUNING PLL FREQUENCY SYNTHESIZER
PRODUCT DESCRIPTION
PRODUCT FEATURES
> 150 Mhz typical input frequency
-163 dBc/Hz total phaswe noise floor
No dead zone, by design
The IMI145152 is a member of a family of phase lock loop
synthesizer Ics from International Microcicruicts. This part is
pin-for-pin compatible with the Motorola MC145152 series of
parts. The IMI145152 is an improved version of this device,
and designing to take advantage of these improvements will
provide a synthesizer with noticeably improved performance.
Unambiguous PLL acquisition
The IMI145152 is programmed with parallel input data lines.
Since it does not require a microcontroller as serial and bus
programming units do, the IMI145152 is an excellent choice
for synthesizers requiring independence from digital
controllers. Such applications particularly include fixed local
oscillator signals, who tuning never changes, and signal
sources, which have few operating frequencies.
Parrallel programming, dual modulus PLL
8 user-selectable reference divider ratios: 8, 64,
128, 256, 512, 1024, 1160, and 2048
Lock detect signal
Blocks in the IMI145152 include a dual modulus feedback
divider for use with an external dual modulus prescaler.
Prescaler ratios can very from 3/4 through 64/65. The
reference divider is set by three select lines to one of eight
ROM encloded values. Both counter inputs are biased for
high sensitivity to sinewave input signals, and the reference
divider input is also configured to operate as an oscillator if
desired. The phase detector is a Type IV phase-frequency
design, which has inherently eliminated the dead zone and
indeed any crossover distortion, as is often noticed on other
PLL devices.
Compatible with dual-modulus prescalers from
÷3/4 to ÷64/65
10-bit N counter, 6-bit A counter
On- or off-chip reference oscillator operation
3-volt and 5-volt characterizations
Performance improvements are in the operating bandwidth
and phase detector noise floor. With its extremely low phase
noise floor and wider input bandwidth, prescaler ratios can
be minimized to allow wide loop bandwidths for faster
settlign and lower phase noise.
BLOCK DIAGRAM
RA2
LOCK
DETECT
6
5
4
28
LD
12
x
8
ROM REFERENCE DECODER
RA1
RA0
OSCin
27
8
7
12 BIT /R COUNTER
CONTROL LOGIC
PHASE DETECTOR
PHIV
PHIR
OSCout 26
1
FIN
9
6
BIT /A COUNTER
10 BIT /N COUNTER
MODULUS CONTROL
VDD
VSS
=
=
PIN
PIN
3
2
10
A5
25
A4
24
A3
22
A2
21
A1
23
A0
11 12 13 14 15 16 17 18 19 20
N0 N1 N2 N3 N4 N5 N6 N7 N8 N9
Note: N0 through N9 have pullup resistors not shown.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
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