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IDTQS32X2861Q18 PDF预览

IDTQS32X2861Q18

更新时间: 2024-11-23 14:51:31
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
5页 54K
描述
Bus Driver, CBT/FST/QS/5C/B Series, 2-Func, 10-Bit, True Output, CMOS, PDSO48, QVSOP-48

IDTQS32X2861Q18 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SSOP,
针数:48Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.92
系列:CBT/FST/QS/5C/BJESD-30 代码:R-PDSO-G48
长度:9.906 mm逻辑集成电路类型:BUS DRIVER
位数:10功能数量:2
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE WITH SERIES RESISTOR输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.7526 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.4 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9116 mm
Base Number Matches:1

IDTQS32X2861Q18 数据手册

 浏览型号IDTQS32X2861Q18的Datasheet PDF文件第2页浏览型号IDTQS32X2861Q18的Datasheet PDF文件第3页浏览型号IDTQS32X2861Q18的Datasheet PDF文件第4页浏览型号IDTQS32X2861Q18的Datasheet PDF文件第5页 
QUICKSWITCH® PRODUCTS  
IDTQS32X2861  
HIGH-SPEED CMOS  
20-BIT BUS SWITCH  
WITH FLOW-THRU PINOUT  
DESCRIPTION:  
FEATURES:  
The QS32X2861 provides two sets of ten high-speed CMOS TTL-  
compatiblebusswitches.ThelowONresistanceoftheQS32X2861allows  
inputs tobe connectedtooutputs withoutaddingpropagationdelayand  
withoutgeneratingadditionalgroundbouncenoise. TheQS32x2861adds  
an internal 25Ω series termination resistor to each switch to reduce  
reflectionnoiseinhigh-speedapplications. TheBusEnable(BEn)signals  
turnthe switches on.  
• Enhanced N channel FET with no inherent diode to Vcc  
• 25Ω series resistors for low noise  
Undershoot clamp diodes on all switch and control inputs  
Available in 48-pin QVSOP package  
APPLICATIONS:  
Hot-swapping, hot-docking  
Voltage translation (5V to 3.3V)  
• Power conservation  
The QS32X2861bus switchis idealforswitchingdigitalbuses,as well  
as for hotplug buffering and 5V to 3V conversion.  
The QS32X2861 is characterized for operation at -40°C to +85°C.  
• Capacitance reduction and isolation  
• Bus isolation  
• Clock gating  
FUNCTIONALBLOCKDIAGRAM  
A0  
B0  
A9  
B9  
BE1  
A10  
B10  
A19  
B19  
BE2  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
MARCH 2002  
1
c
2002 Integrated Device Technology, Inc.  
DSC-5727/3  

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