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IDTQS32XR384Q1 PDF预览

IDTQS32XR384Q1

更新时间: 2024-11-23 14:51:31
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
5页 87K
描述
Bus Driver, 2-Func, 10-Bit, True Output, CMOS, PDSO48, QVSOP-48

IDTQS32XR384Q1 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SSOP,针数:48
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
其他特性:BUS SWITCHJESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:9.906 mm
逻辑集成电路类型:BUS DRIVER位数:10
功能数量:2端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH传播延迟(tpd):0.12 ns
认证状态:Not Qualified座面最大高度:1.7526 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.4 mm端子位置:DUAL
宽度:3.9116 mmBase Number Matches:1

IDTQS32XR384Q1 数据手册

 浏览型号IDTQS32XR384Q1的Datasheet PDF文件第2页浏览型号IDTQS32XR384Q1的Datasheet PDF文件第3页浏览型号IDTQS32XR384Q1的Datasheet PDF文件第4页浏览型号IDTQS32XR384Q1的Datasheet PDF文件第5页 
QUICKSWITCH® PRODUCTS  
IDTQS32XR384  
HIGH-SPEED CMOS 20-BIT LOW  
RESISTANCE BUS SWITCH  
DESCRIPTION:  
FEATURES:  
Enhanced N channel FET with no inherent diode to Vcc  
2.5bidirectional switches connect inputs to outputs  
Zero propagation delay, zero ground bounce  
Undershoot clamp diodes on all switch and control pins  
Two enables control five bits each  
The QS32XR384 provides two sets of ten high-speed CMOS TTL-  
compatible bus switches. Four banks of five switches are controlled by  
independentBusEnable(BE)signals. TheverylowRON resistance(2.5)  
oftheQS32XR384allows inputs tobeconnectedwithoutaddingpropaga-  
tiondelayandwithoutgeneratingadditionalgroundbounce noise.  
Available in 48-pin QVSOP Package  
The QS32XR384is idealforswitchingdigitalbuses, as wellas forhot  
plug buffering and 5V to 3.3V conversion.  
APPLICATIONS  
The QS32XR384 is characterized for operation at -40°C to +85°C.  
Hot-swapping and hot-docking (low resistance for PCI and  
Compact PCI applications)  
Voltage translation (5V to 3.3V)  
Power conservation  
Capacitance reduction and isolation  
Bus isolation  
Clock gating  
FUNCTIONALBLOCKDIAGRAM  
A10  
B10  
A0  
B0  
A14  
A15  
A4  
A5  
B14  
B15  
B4  
B5  
A19  
B19  
A9  
B9  
BEA  
BEC  
BED  
BEB  
INDUSTRIAL TEMPERATURE RANGE  
NOVEMBER 1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-5548/-  

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