Datasheet > IDTCV193CPAG8

IDTCV193CPAG8

更新时间： 2024-11-16 05:39:07

品牌	Logo	应用领域
艾迪悌 - IDT		PC 时钟
页数	文件大小	规格书
21页	177K
描述
PROGRAMMABLE FLEXPC LP/S CLOCK FOR INTEL BASED SYSTEMS

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中文翻译

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数据手册

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IDTCV193CPAG8 数据手册

IDTCV193

COMMERCIALTEMPERATURERANGE

PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR

PROGRAMMABLE FLEXPC

LP/S CLOCK FOR INTEL BASED

SYSTEMS

IDTCV193

ADVANCE

INFORMATION

FEATURES:

KEYFEATURES

• Compliant with Intel CK505 Gen II spec

• One high precision PLL for CPU, SSC and N programming

• One high precision PLL for SRC, SSC and N programming

• One high precision PLL for SATA/PCI, and SSC

• One high precision PLL for 96MHz/48MHz

• Push-pull IOs for differential outputs

• Direct CPU and SRC clock frequency programming—write the

Hex number into Byte [16:18], 1MHz stepping.

• Linear and smooth transition for the CPU and SRC frequency

programming.

• SATA PLL source hardware select latch pin, PLL2 or PLL4.

• Internal serial resistor hardware enable latch pin.

• Support spread spectrum modulation, –0.5 down spread and • WOL 25MHz support.

others

• Support SMBus block read/write, byte read/write

• Available in TSSOP package

OUTPUTS:

KEY SPECIFICATIONS:

• 2 - 0.7V differential CPU CLK pair

• 10 - 0.7V differential SRC CLK pair

• 1 - CPU_ITP/SRC differential clock pair

• 1 - SRC0/DOT96 differential clock pair

• 6 - PCI, 33.3MHz

• CPU/SRC CLK cycle to cycle jitter < 85ps

• PCI CLK cycle to cycle jitter < 500ps

• All SRC, SRC[0:11] phase noise < 3.10s RMS, PCIE Gen II

phase noise requirement.

• SRC3, 4, 6, 7, designated PCIE Gen II outputs, nominal

interpair skew = 0 ps

• 1 - 48MHz

• 1 - REF

• 1 - SATA

FUNCTIONALBLOCKDIAGRAM

REF

PLL1

SSC

N Programmable

XTAL_IN

XTAL

CPU[1:0]

CPU

Output Buffer

Stop Logic

Osc Amp

XTAL_OUT

CPU_ITP/SRC8

SDATA

SM Bus

PLL3

SSC

SRC1/25MHz/24.576MHz

PCI[4:0], PCIF5

Controller

PCI/SATA

SRC CLK

SCLK

Output Buffer

Stop Logic

SATA/SRC2

PLL4

SSC

N Programmable

SRC CLK

Output Buffer

Stop Logic

SRC[7:3], [11:9]

CKPWRGD/PD#

CPU_STOP#

PCI_STOP#

SRC5_EN

48MHz

Control

ITP_EN

Logic

Fixed PLL

PLL2

48MHz/96MHz

Output BUffer

CR_[H:A]#

DOT96/SRC0

FSC,B,A

SATA_SEL

SR_ENABLE

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL TEMPERATURE RANGE

APRIL 8, 2009

IDT CONFIDENTIAL

DSC 7165

12 3 4 5 6 7...21

中文翻译

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与IDTCV193CPAG8相关器件

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IDTCV193CPVG8	IDT	获取价格	PROGRAMMABLE FLEXPC LP/S CLOCK FOR INTEL BASED SYSTEMS
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