Datasheet > IDTIDT71P71804200BQ

IDTIDT71P71804200BQ

更新时间： 2024-11-16 02:54:55

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器双倍数据速率
页数	文件大小	规格书
23页	229K
描述
18Mb Pipelined DDR⑩II SRAM Burst of 2

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18Mb Pipelined

DDR™II SRAM

Burst of 2

IDT71P71804

IDT71P71604

Description

Features

The IDT DDRII^TMBurst of two SRAMs are high-speed synchro-

nous memories with a double-data-rate (DDR), bidirectional data port.

This scheme allows maximization of the bandwidth on the data bus by

passing two data items per clock cycle. The address bus operates at

single data rate speeds, allowing the user to fan out addresses and

ease system design while maintaining maximum performance on data

transfers.

◆

18Mb Density (1Mx18, 512kx36)

Common Read and Write Data Port

Dual Echo Clock Output

2-Word Burst on all SRAM accesses

MultiplexedAddress Bus

One Read or One Write request per clock cycle

◆

DDR (Double Data Rate) Data Bus

The DDRII has scalable output impedance on its data output bus

and echo clocks, allowing the user to tune the bus for low noise and high

performance.

Two word bursts data per clock

◆

Depth expansion through Control Logic

HSTL (1.5V) inputs that can be scaled to receive signals from

1.4V to 1.9V.

All interfaces of the DDRII SRAM are HSTL, allowing speeds

beyond SRAM devices that use any form of TTL interface. The inter-

face can be scaled to higher voltages (up to 1.9V) to interface with 1.8V

systems if necessary. The device has a VDDQ and a separate Vref,

allowing the user to designate the interface operational voltage, inde-

pendent of the device core voltage of 1.8V VDD. Theoutput impedance

control allows the user to adjust the drive strength to adapt to a wide

range of loads and transmission lines.

◆

Scalable output drivers

Can drive HSTL, 1.8V TTL or any voltage level

from 1.4V to 1.9V.

Output Impedance adjustable from 35 ohms to 70

ohms

◆

1.8V Core Voltage (VDD)

165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package

JTAG Interface

Clocking

The DDRII SRAM has two sets of input clocks, namely the K, K

clocks and the C, Cclocks. In addition, the DDRII has an output “echo”

clock, CQ, CQ.

Functional Block Diagram

DATA

REG

(Note 1)

WRITE DRIVER

(Note2)

ADD

REG

(Note2)

(Note1)

(Note4)

(Note1)

18M

MEMORY

ARRAY

R/W

BWx

CTRL

LOGIC

(Note3)

CLK

GEN

SELECT OUTPUT CONTROL

6112 drw 16

Notes

1) Represents 18 signal lines for x18, and 36 signal lines for x36

2) Represents 20 address signal lines for x18 and 19 address signal lines for x36.

3) Represents 2 signal lines for x18 and 4 signal lines for x36.

4) Represents 36 signal lines for x18 and 72 signal lines for x36.

APRIL 2006

DSC-6112/0A

12 3 4 5 6 7...23

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与IDTIDT71P71804200BQ相关器件

型号	品牌	获取价格	描述	数据表
IDTIDT71P71804250BQ	IDT	获取价格	18Mb Pipelined DDR⑩II SRAM Burst of 2
IDTIDT71P79104167BQ	IDT	获取价格	18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79104167BQI	IDT	获取价格	18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79104200BQ	IDT	获取价格	18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79104200BQI	IDT	获取价格	18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79104250BQ	IDT	获取价格	18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79104250BQI	IDT	获取价格	18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79104267BQ	IDT	获取价格	18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79104267BQI	IDT	获取价格	18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
IDTIDT71P79204167BQ	IDT	获取价格	18Mb Pipelined DDR⑩II SIO SRAM Burst of 2

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