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IDT79RV4650100MS PDF预览

IDT79RV4650100MS

更新时间: 2024-11-11 23:01:19
品牌 Logo 应用领域
艾迪悌 - IDT 微处理器
页数 文件大小 规格书
25页 501K
描述
EMBEDDED 64-BIT ORION ? RISC MICROPROCESSOR

IDT79RV4650100MS 数据手册

 浏览型号IDT79RV4650100MS的Datasheet PDF文件第2页浏览型号IDT79RV4650100MS的Datasheet PDF文件第3页浏览型号IDT79RV4650100MS的Datasheet PDF文件第4页浏览型号IDT79RV4650100MS的Datasheet PDF文件第5页浏览型号IDT79RV4650100MS的Datasheet PDF文件第6页浏览型号IDT79RV4650100MS的Datasheet PDF文件第7页 
IDT79RC4650™  
Low-Cost 64-bit  
RISController  
w/DSP Capability  
Large, efficient on-chip caches  
)HDWXUHV  
Separate 8kB Instruction and 8kB Data caches  
Over 3200MB/sec bandwidth from internal caches  
2-set associative  
Write-back and write-through support  
Cache locking to facilitate deterministic response  
High-performance embedded 64-bit microprocessor  
64-bit integer operations  
64-bit registers  
100MHz, 133MHz, 150 MHz, 180MHz, 200MHz and 267MHz  
operation frequencies  
Bus compatible with RC4000 family  
High-performance DSP capability  
System interface provides bandwidth up to 1000 MB/S  
Direct interface to 32-bit wide or 64-bit wide systems  
Synchronized to external reference clock for multi-master  
operation  
133.5 Million Integer Multiply-Accumulate Operations/sec @  
267 MHz  
High-performance microprocessor  
133.5 M Mul-Add/second at 267MHz  
89 MFL0P/s at 250MHz  
>640,000 dhrystone (2.1)/sec capability at 267MHz  
Socket compatible with IDT RC64475 and RC64575  
Improved real-time support  
Fast interrupt decode  
(352 dhrystone MIPS)  
High level of integration  
Optional cache locking  
Note:“R” refers to 5V parts; “RVrefers to 3.3V parts; “RC”  
refers to both  
64-bit, 267 MHz integer CPU  
8KB instruction cache; 8KB data cache  
Integer multiply unit with 133.5M Mul-Add/sec  
Low-power operation  
Active power management powers-down inactive units  
Standby mode  
Upwardly software compatible with IDT RISController  
Family  
%ORFN#'LDJUDP  
352 M IPS 64-bit C PU  
System C ontrol C oprocessor  
89M FL O PS Single-Precision FPA  
FP register file  
Address Translation/  
Cache Attribute Control  
64-bit register file  
64-bit adder  
Load aligner  
Store Aligner  
Logic Unit  
Pack/Unpack  
Exception M anagem ent  
Functions  
FP Add/Sub/C vt/  
Div/Sqrt  
H igh-Perform ance  
Integer M ultiply  
FP M ultiply  
Control Bus  
Data Bus  
Instruction Bus  
Instruction Cache  
Set A  
(Lockable)  
Data Cache  
Set A  
(Lockable)  
Instruction Cache  
Set B  
32-/64-bit  
Synchronized  
System Interface  
D ata C ache  
Set  
B
The IDT logo is a registered trademark and ORION, RC4600, RC4650, RV4650, RC4700, RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.  
1 of 25  
March 28, 2000  
DSC 3149/3  
2000 Integrated Device Technology, Inc.  

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