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IDT79RC32V364-133DA PDF预览

IDT79RC32V364-133DA

更新时间: 2024-11-20 23:58:27
品牌 Logo 应用领域
其他 - ETC 外围集成电路微处理器时钟
页数 文件大小 规格书
21页 483K
描述
32-Bit Microprocessor

IDT79RC32V364-133DA 数据手册

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79RC32364™  
RISControllerTM Embedded 32-bit  
Microprocessor, based on  
RISCore32300  
Flexible RC4000 compatible MMU with 32-page TLB on-chip  
Features  
Variable page size  
High-performance embedded RISControllerTM  
Variable number of locked entries  
No performance penalty for address translation  
microprocessor, based on IDT RISCore32300TM 32-bit CPU  
core  
Flexible bus interface allows simple, low-cost designs  
Based on MIPS 32 RISC architecture with enhancements  
Scalar 5-stage pipeline minimizes branch and load delays  
66 Million multiply accumulate (MAC) Mul-Add/second  
@ 133MHz  
Bus interface runs at a fraction of pipeline rate  
Programmable port-width interface (8-,16-, 32-bit memory and  
I/O regions)  
Programmable bus turnaround times (BTA)  
Supports single data or burst transactions  
100 and 133 frequencies  
MIPS 32 (ISA) instruction set architecture  
Improved real-time support  
MIPS IV compatible conditional move instructions  
MIPS IV superset PREF (prefetch) instruction  
Fast multiplier with atomic multiply-add, multiply-sub  
Count leading zeros/ones instructions  
Fast interrupt decode  
Low-power operation  
Active power management: powers down inactive units  
Typical power 700mW @ 133MHz  
Large, efficient on-chip caches  
Stand-by mode <300mW  
Separate 8kB Instruction cache and 2kB Data cache  
2-way set associative  
Enhanced JTAG interface, for low-cost in-circuit emulation  
(ICE)  
Write-back and write-through support on a per page basis  
Optional cache locking with “per line” resolution, to facilitate  
deterministic response  
MIPS architecture ensures applications software  
compatibility throughout the RISController series of  
embedded processors  
Simultaneous instruction and data fetch in each clock cycle,  
sustained rate, achieves over 1 GB/sec bandwidth  
Industrial temperature range support  
3.3V operation (core and I/O)  
Block Diagram  
RISCore32300TM  
Extended MIPS 32  
Integer CPU Core  
RISCore4000 Compatible  
System Control  
MMU  
w/  
Coprocessor (CPO)  
TLB  
8kB  
I-Cache,  
lockable  
2kB D-Cache, 2-set,  
2-set,  
lockable, write-back/write-through  
RISCore32300 Internal Bus Interface  
RC32364 Bus Interface Unit  
Clock  
Generation  
Unit  
The IDT logo is a registered trademark and ORION, RC4650, RC4640, RV4640, RC4600, RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.  
1 of 21  
June 20, 2000  
DSC 4510  
2000 Integrated Device Technology, Inc.  
*Notice: The information in this document is subject to change without notice  

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