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IDT79R3081E-20MJ PDF预览

IDT79R3081E-20MJ

更新时间: 2024-11-20 22:23:47
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
38页 297K
描述
RISController with FPA

IDT79R3081E-20MJ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFN包装说明:QCCJ, LDCC84,1.2SQ
针数:84Reach Compliance Code:not_compliant
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.82其他特性:CACHE COHERENCY
地址总线宽度:32位大小:32
边界扫描:NO最大时钟频率:40 MHz
外部数据总线宽度:32格式:FLOATING POINT
集成缓存:NOJESD-30 代码:S-PQCC-J84
JESD-609代码:e0长度:29.083 mm
低功率模式:YES湿度敏感等级:1
DMA 通道数量:外部中断装置数量:6
串行 I/O 数:端子数量:84
片上数据RAM宽度:最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC84,1.2SQ
封装形状:SQUARE封装形式:CHIP CARRIER
电源:5 V认证状态:Not Qualified
RAM(字数):0座面最大高度:4.57 mm
速度:20 MHz子类别:Microprocessors
最大压摆率:475 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:29.083 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR, RISCBase Number Matches:1

IDT79R3081E-20MJ 数据手册

 浏览型号IDT79R3081E-20MJ的Datasheet PDF文件第2页浏览型号IDT79R3081E-20MJ的Datasheet PDF文件第3页浏览型号IDT79R3081E-20MJ的Datasheet PDF文件第4页浏览型号IDT79R3081E-20MJ的Datasheet PDF文件第5页浏览型号IDT79R3081E-20MJ的Datasheet PDF文件第6页浏览型号IDT79R3081E-20MJ的Datasheet PDF文件第7页 
IDT 79R3081 , 79R3081E  
IDT79R3081  
RISController  
with FPA  
IDT 79RV3081, 79RV3081E  
Integrated Device Technology, Inc.  
• Large on-chip caches with user configurability  
— 16kB Instruction Cache, 4kB Data Cache  
— Dynamically configurable to 8kB Instruction Cache,  
8kB Data Cache  
— Parity protection over data and tag fields  
• Low cost 84-pin packaging  
• Superset pin- and software-compatible with R3051, R3071  
• Multiplexed bus interface with support for low-cost, low-  
speed memory systems with a high-speed CPU  
• On-chip 4-deep write buffer eliminates memory write stalls  
• On-chip 4-deep read buffer supports burst or simple block  
reads  
FEATURES  
• Instruction set compatible with IDT79R3000A, R3041,  
R3051, and R3071 RISC CPUs  
• High level of integration minimizes system cost  
— R3000A Compatible CPU  
— R3010A Compatible Floating Point Accelerator  
— Optional R3000A compatible MMU  
— Large Instruction Cache  
— Large Data Cache  
— Read/Write Buffers  
• 43VUPS at 50MHz  
— 13MFlops  
• Flexible bus interface allows simple, low cost designs  
• Optional 1x or 2x clock input  
• 20 through 50MHz operation  
• On-chip DMA arbiter  
• Hardware-based Cache Coherency Support  
• Programmable power reduction mode  
• Bus Interface can operate at half-processor frequency  
• "V" version operates at 3.3V  
• 50MHz at 1x clock input and 1/2 bus frequency only  
R3081 BLOCK DIAGRAM  
BrCond(3:2,0)  
Master Pipeline Control  
ClkIn  
Clock Generator  
Unit/Clock Doubler  
System Control  
Coprocessor  
(CP0)  
Floating Point  
Coprocessor  
(CP1)  
Integer  
CPU Core  
Exception/Control  
Registers  
General Registers  
(32 x 32)  
Register Unit  
(16 x 64)  
Memory Management  
Registers  
ALU  
Shifter  
Exponent Unit  
Add Unit  
Divide Unit  
Multiply Unit  
Mult/Div Unit  
Translation  
Lookaside Buffer  
(64 entries)  
Int(5:0)  
Address Adder  
PC Control  
Exception/Control  
Virtual Address  
FP Interrupt  
Data Bus  
Physical Address Bus  
32  
Configurable  
Instruction  
Cache  
Configurable  
Data  
36  
Cache  
(4kB/8kB)  
(16kB/8kB)  
Data Bus  
Parity  
Generator  
R3051 Superset Bus Interface Unit  
4-deep  
Read  
Buffer  
4-deep  
Write  
Buffer  
DMA  
Arbiter  
BIU  
Control  
Coherency  
Logic  
Address/  
Data  
DMA  
Ctrl  
Rd/Wr  
Ctrl  
SysClk Invalidate  
Control  
2889 drw 01  
The IDT logo is a registered trademark, and RISController, R3041, R3051, R3052, R3071, R3081, R3720, R4400, R4600, IDT/kit, and IDT/sim are trademarks of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
SEPTEMBER 1995  
1995 Integrated Device Technology, Inc.  
5.5  
DSC-9064/4  
1

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