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IDT77V1253L25PGI PDF预览

IDT77V1253L25PGI

更新时间： 2024-01-29 09:34:03
品牌 Logo 应用领域
艾迪悌 - IDT ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
44页 449K
描述
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6 AND 51.2 MBPS ATM NETWORKS

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IDT77V1253L25PGI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：QFP, QFP144,1.2SQ
针数：144Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.29
应用程序：ATMJESD-30 代码：S-PQFP-G144
JESD-609代码：e0长度：28 mm
功能数量：1端子数量：144
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP144,1.2SQ封装形状：SQUARE
封装形式：FLATPACK峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
座面最大高度：4.07 mm子类别：ATM/SONET/SDH ICs
最大压摆率：0.14 mA标称供电电压：3.3 V
表面贴装：YES技术：CMOS
电信集成电路类型：ATM/SONET/SDH NETWORK INTERFACE温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：28 mm
Base Number Matches：1

IDT77V1253L25PGI 数据手册

 浏览型号IDT77V1253L25PGI的Datasheet PDF文件第7页浏览型号IDT77V1253L25PGI的Datasheet PDF文件第8页浏览型号IDT77V1253L25PGI的Datasheet PDF文件第9页浏览型号IDT77V1253L25PGI的Datasheet PDF文件第11页浏览型号IDT77V1253L25PGI的Datasheet PDF文件第12页浏览型号IDT77V1253L25PGI的Datasheet PDF文件第13页 
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6  
AND 51.2 MBPS ATM NETWORKS  
IDT77V1253  
The 77V1253 is based on the 77105, and maintains significant register  
compatibilitywithit.The77V1253,however,hasadditionalregisterfeatures,  
andalsoduplicatesmostofitsregisterstoprovidesignificantindependence  
betweenthethreeports.  
Accesstothesestatusandcontrolregistersisthroughtheutilitybus. This  
is an 8-bit muxed address and data bus, controlled by a conventional  
asynchronousread/writehandshake.  
77V1253OVERVIEW:  
The77V1253isathree-portimplementationofthephysicallayerstandard  
for 25.6Mbps ATM network communications as defined by ATM Forum  
document af-phy-040.000 and ITU-T I.432.5. The physical layer is divided  
intoaPhysicalMediaDependentsublayer(PMD)andTransmissionConver-  
gence (TC) sub layer. The PMD sub layer includes the functions for the  
transmitter, receiverandclockrecoveryforoperationacross 100meters of  
category3unshieldedtwistedpair(UTP)cable.ThisisreferredtoastheLine  
Side Interface. The TC sub layer defines the line coding, scrambling, data  
framingandsynchronization.  
Additionalpinspermitinsertionandextractionofan8kHztimingmarker,and  
provideLEDindicationofreceiveandtransmitstatus.  
OPERATIONAT51.2Mbps  
Inadditiontooperationatthestandardrateof25.6Mbps,the77V1253is  
alsospecifiedtooperateat51.2Mbps. Exceptforthedoubledbitrate,allother  
aspects of operation are identical to the 25.6 Mbps mode. The data rate is  
determinedbythefrequencyoftheclockappliedtotheOSCinput. OSCis32  
MHz for the 25.6 Mbps line rate, and 64 MHz for the 51.2 Mbps line rate. All  
portsoperateatthesamefrequency.  
Onthe otherside, the 77V1253interfaces toanATMlayerdevice (such  
asaswitchcoreorSAR). Thiscelllevelinterfaceisconfigurableaseither8-  
bit Utopia Level 1 Multi-PHY, 16-bit Utopia Level 2, or as three 4-bit DPI  
interfaces,asdeterminedbytwoMODEpins. ThisisreferredtoasthePHY-  
ATM Interface. The pinout and front page block diagram are based on the  
Utopia2configuration.Table2showsthecorrespondingpinfunctionsforthe  
othertwomodes, andFigures 2and3showfunctionalblockdiagrams.  
See page 30 for recommended line magnetics. Magnetics for 51.2 Mbps  
operationhaveahigherbandwidththanmagneticsoptimizedfor25.6Mbps.  
TxREF  
TxCLK  
+
-
Driver  
Tx Port 0  
Rx Port 0  
TxDATA[7:0]  
5B/4B  
Encoding/  
Decoding  
TxParity  
TxSOC  
TxEN[2:0]  
TxCLAV[2:0]  
Tx/Rx ATM  
Cell FIFO  
Scrambler/  
Descrambler  
P/S and S/P  
NRZI  
Clock/Data  
Recovery  
+
-
UTOPIA  
Multi-PHY  
Interface  
Mode[1:0]  
RxCLK  
RxDATA[7:0]  
RxParity  
+
-
Driver  
Tx Port 1  
Rx Port 1  
5B/4B  
Encoding/  
Decoding  
RxSOC  
Tx/Rx ATM  
Cell FIFO  
Scrambler/  
Descrambler  
P/S and S/P  
NRZI  
RxEN[2:0]  
Clock/Data  
Recovery  
+
-
RxCLAV[2:0]  
INT  
RST  
RD  
WR  
+
-
Microprocessor  
(Utility Bus)  
Interface  
Tx Port 2  
Rx Port 2  
Driver  
5B/4B  
Encoding/  
Decoding  
Tx/Rx ATM  
Cell FIFO  
Scrambler/  
Descrambler  
P/S and S/P  
NRZI  
CS  
+
-
Clock/Data  
Recovery  
AD[7:0]  
ALE  
3
3
OSC  
RxREF  
4781 drw 03  
RxLED[2:0] TxLED[2:0]  
Figure 2. Block Diagram for Utopia Level 1 configuration (MODE[1:0] = 01)  
10  
1...78910111213...44

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