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IDT74LVC273AQ8 PDF预览

IDT74LVC273AQ8

更新时间: 2024-11-13 19:57:39
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
5页 91K
描述
D Flip-Flop, LVC/LCX/Z Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20, QSOP-20

IDT74LVC273AQ8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QSOP包装说明:SSOP,
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.87
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G20
长度:8.65 mm逻辑集成电路类型:D FLIP-FLOP
位数:8功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):9.5 ns认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:3.9116 mmBase Number Matches:1

IDT74LVC273AQ8 数据手册

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3.3V CMOS OCTAL D-TYPE  
FLIP-FLOP WITH RESET,  
IDT74LVC273A  
POSITIVE EDGE TRIGGER,  
AND 5 VOLT TOLERANT I/O  
DESCRIPTION:  
FEATURES:  
0.5 MICRON CMOS Technology  
The octalD-type flip-flopwithreset,positive edge triggeris builtusing  
advanced dual metal CMOS technology. This high-speed, low power  
deviceisidealfordrivinghighcapacitanceloadssuchasmemoryaddress  
anddata buses.  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
1.27mm pitch SOIC, 0.65mm pitch SSOP,  
0.635mm pitch QSOP, 0.65mm pitch TSSOP packages  
Extended commercial range of – 40°C to +85°C  
VCC = 3.3V ±0.3V, Normal Range  
Allpinscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows  
theuseofthesedevices as translators inamixed3.3V/5Vsupplysystem.  
VCC = 2.3V to 3.6V, Extended Range  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
All inputs, outputs and I/O are 5 Volt tolerant  
Supports hot insertion  
Drive Features for LVC273A:  
APPLICATIONS:  
• 5V and 3.3V mixed voltage systems  
Data communication and telecommunication systems  
High Drive Output: ±24mA  
Reduced system switching noise  
FUNCTIONALBLOCKDIAGRAM  
PINCONFIGURATION  
D
x
Ox  
Q
D
1
2
3
CLR  
O0  
20  
19  
18  
17  
CC  
V
CP  
CP  
CLR  
O7  
D7  
D6  
O6  
D0  
4
5
D1  
CLR  
SO20-2  
SO20-7  
SO20-8  
SO20-9  
O1  
16  
15  
14  
13  
12  
PIN DESCRIPTION  
6
O2  
O5  
D5  
Pin Names  
Description  
Clear Input  
Clock Input  
Data Outputs  
Data Inputs  
CLR  
CP  
Ox  
Dx  
7
2
D
8
D3  
O3  
D4  
O4  
9
10  
GND  
11  
CP  
FUNCTION TABLE (1)  
SOIC/ SSOP/ QSOP/ TSSOP  
TOP VIEW  
Inputs  
CP  
Internal  
Q Value  
Outputs  
Ox  
CLR  
L
Dx  
X
L
Function  
X
L
L
H
L
L
H
Clear Register  
Load Input Data  
Load Input Data  
H
H
H
NOTE:  
1. H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Don’t Care  
= LOW-to-HIGH Transition  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
AUGUST 1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-4595/-  

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