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IDT74FCT32932-100 PDF预览

IDT74FCT32932-100

更新时间: 2024-11-15 22:36:11
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器
页数 文件大小 规格书
9页 135K
描述
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER

IDT74FCT32932-100 数据手册

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IDT74FCT3932-100  
IDT74FCT32932-100  
ADVANCE INFORMATION  
3.3V LOW SKEW PLL-BASED  
CMOS CLOCK DRIVER  
Integrated Device Technology, Inc.  
feedbackpathdelayshouldbemadetomatchthisoutputpath  
delay.  
The PLL consists of the phase/frequency detector, charge  
pump, loopfilterandVCO. TheFCT3932requiresnoexternal  
loop filter components.  
The FCT3932 provides 17 outputs grouped in 3 banks with  
individual 3-state control and an additional dedicated feed-  
backoutputwithnodisable. ConnectingQ_FBtoFEEDBACK  
ensures uninterrupted PLL operation when all outputs are  
disabled.  
Individual bank 3-state allows users to disable unused  
outputs in order to limit power dissipation or minimize switch-  
ing noise. It also allows users to shut down outputs in low  
power modes while maintaining phase lock.  
TheFCT3932providesaLOCKpinthatgoeshighwhenthe  
device is phase-locked.  
The user can bypass the PLL for testability purposes by  
deasserting PLL_EN. In this "test" mode, the input frequency  
is not limited to the specified range.  
The FCT3932 provides an asynchronous reset input, RST,  
whichresetsalloutputs. Thisinitializesallinternalregistersso  
that outputs start up in a known state.  
FEATURES:  
0.5 MICRON CMOS Technology  
• Guaranteed low skew  
• 16 programmable frequency configurations  
• 17 3-state outputs:  
±24 mA FCT3932  
±8 mA FCT32932  
• Output configuration:  
BANK1: 4 outputs  
BANK2: 8 outputs  
BANK3: 5 outputs  
• Dedicated feedback output (Q_FB)  
• Maximum output frequency: 100MHz  
• VCC = 3.3V ±0.3V  
• Inputs can be driven from 3.3V or 5V components  
• Available in 48 SSOP, TSSOP packages  
• Suited to SDRAM applications  
DESCRIPTION:  
The FCT3932 uses phase-lock loop technology to lock the  
frequency and phase of the feedback to the input reference  
clock. It provides a large number of low skew outputs that are  
configurable in 16 different modes using the CNTRL 1-4  
inputs. A dedicated output, Q_FB, is provided to supply the  
PLL feedback and it should be connected to the FEEDBACK  
input. Q_FB is located adjacent to FEEDBACK to minimize  
the delay in the feedback path. In order to offset any delay in  
theoutputpathfromtheFCT3932outputtoareceivingdevice,  
APPLICATIONS:  
SDRAM DIMM Clock, Caches, high speed microproces-  
sors, motherboard clock distribution to DIMMs.  
FUNCTIONAL BLOCK DIAGRAM  
LOCK  
FEEDBACK  
Voltage  
Controlled  
Oscillator  
Charge  
Pump &  
Loop Filter  
Phase/Freq.  
Detector  
REF_IN  
0
1
PLL_EN  
Mux  
OE1  
OE2  
Q41-4  
(BANK 1)  
C
O
N
T
R
O
L
Q81-8  
(BANK 2)  
OE3  
Q51-5  
(BANK 3)  
CNTRL1-4  
Q_FB  
RST  
3267 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL TEMPERATURE RANGE  
NOVEMBER 1996  
1996 Integrated Device Technology, Inc.  
9.9  
DSC-3267/2  
1

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