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IDT74FCT16260ATPFG PDF预览

IDT74FCT16260ATPFG

更新时间: 2024-10-28 21:16:27
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管逻辑集成电路电视
页数 文件大小 规格书
8页 116K
描述
Bus Exchanger, FCT Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, TVSOP-56

IDT74FCT16260ATPFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:TVSOP-56针数:56
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.68系列:FCT
JESD-30 代码:R-PDSO-G56JESD-609代码:e3
长度:11.3 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS EXCHANGER湿度敏感等级:1
位数:12功能数量:1
端口数量:3端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):5.2 ns
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.4 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

IDT74FCT16260ATPFG 数据手册

 浏览型号IDT74FCT16260ATPFG的Datasheet PDF文件第2页浏览型号IDT74FCT16260ATPFG的Datasheet PDF文件第3页浏览型号IDT74FCT16260ATPFG的Datasheet PDF文件第4页浏览型号IDT74FCT16260ATPFG的Datasheet PDF文件第5页浏览型号IDT74FCT16260ATPFG的Datasheet PDF文件第6页浏览型号IDT74FCT16260ATPFG的Datasheet PDF文件第7页 
FAST CMOS  
IDT54/74FCT16260AT/CT/ET  
12-BIT TRI-PORT  
BUS EXCHANGER  
DESCRIPTION:  
FEATURES:  
0.5 MICRON CMOS Technology  
The FCT16260T Tri-Port Bus Exchangers are high-speed 12-bit  
latchedbusmultiplexers/transceiversforuseinhigh-speedmicroprocessor  
applications. These Bus Exchangers support memory interleaving with  
latchedoutputsontheBportsandaddressmultiplexingwithlatchedinputs  
on the B ports.  
High-speed, low-power CMOS replacement for ABT functions  
Typical tSK(o) (Output Skew) < 250ps  
Low input and output leakage 1µA (max.)  
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
The Tri-Port Bus Exchanger has three 12-bit ports. Data may be  
transferred between the A port and either/both of the B ports. The latch  
enable (LE1B, LE2B, LEA1B and LEA2B) inputs control data storage.  
Whena latch-enable inputis high,the latchis transparent. Whena latch-  
enableinputislow,thedataattheinputislatchedandremainslatcheduntil  
thelatchenableinputisreturnedhigh. Independentoutputenables(OE1B  
and OE2B) allow reading from one port while writing to the other port.  
VCC = 5V ±10%  
High drive outputs (-32mA IOH, 64mA IOL)  
Power off disable outputs permit live insertion”  
Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA =  
25°C  
Power off disable outputs permit live insertion”  
Available in the following packages:  
TheFCT16260Tisideallysuitedfordrivinghighcapacitanceloadsand  
lowimpedance backplanes. The outputbuffers are designedwithpower  
off disable capability to allow "live insertion" of boards when used as  
backplane drivers.  
Industrial: SSOP, TSSOP, TVSOP  
Military: CERPACK  
FUNCTIONALBLOCKDIAGRAM  
29  
OE1B  
30  
LEA1B  
A-1B  
LATCH  
1B1:12  
12  
2
LE1B  
1B-A  
12  
LATCH  
12  
12  
28  
SEL  
1
OEA  
1
M
1:12  
A
U
12  
X
0
12  
12  
2B-A  
27  
LATCH  
12  
LE2B  
A-2B  
LATCH  
55  
1:12  
2B  
12  
LEA2B  
56  
OE2B  
MILITARY AND INDUSTRIAL TEMPERATURE RANGES  
JUNE 2000  
1
c
1999 Integrated Device Technology, Inc.  
DSC-5431/-  

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