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IDT74FCT162543TEG PDF预览

IDT74FCT162543TEG

更新时间: 2024-10-28 19:58:47
品牌 Logo 应用领域
艾迪悌 - IDT 输出元件逻辑集成电路
页数 文件大小 规格书
7页 131K
描述
Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, CDFP56, 0.635 MM PITCH, CERPACK-56

IDT74FCT162543TEG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DFP
包装说明:DFP,针数:56
Reach Compliance Code:compliant风险等级:5.73
其他特性:INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH系列:FCT
JESD-30 代码:R-GDFP-F56JESD-609代码:e3
长度:18.415 mm负载电容(CL):50 pF
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER位数:8
功能数量:2端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):260
传播延迟(tpd):12.5 ns认证状态:Not Qualified
座面最大高度:2.143 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:FLAT端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:9.652 mmBase Number Matches:1

IDT74FCT162543TEG 数据手册

 浏览型号IDT74FCT162543TEG的Datasheet PDF文件第2页浏览型号IDT74FCT162543TEG的Datasheet PDF文件第3页浏览型号IDT74FCT162543TEG的Datasheet PDF文件第4页浏览型号IDT74FCT162543TEG的Datasheet PDF文件第5页浏览型号IDT74FCT162543TEG的Datasheet PDF文件第6页浏览型号IDT74FCT162543TEG的Datasheet PDF文件第7页 
FAST CMOS  
IDT54/74FCT162543T/AT/CT/ET  
16-BIT LATCHED  
TRANSCEIVER  
FEATURES:  
DESCRIPTION:  
0.5 MICRON CMOS Technology  
High-speed, low-power CMOS replacement for ABT functions  
Typical tSK(o) (Output Skew) < 250ps  
Low input and output leakage 1µA (max.)  
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP  
and 25 mil pitch CERPACK packages  
The FCT162543T/AT/CT/ET 16-bit latched transceivers are built  
using advanced dual metal CMOS technology. These high-speed, low-  
power devices are organized as two independent 8-bit D-type latched  
transceivers withseparate inputandoutputcontroltopermitindependent  
control of data flow in either direction. For example, the A-to-B Enable  
(xCEAB)mustbelowinordertoenterdatafromtheAportortooutputdata  
fromtheBport. xLEABcontrols thelatchfunction.WhenxLEABis low,the  
latches are transparent. A subsequent low-to-high transition of xLEAB  
signal puts the A latches in the storage mode. xOEAB performs output  
enablefunctionontheBport.DataflowfromtheBporttotheAportissimilar  
but requires using xCEBA, xLEBA, and xOEBA inputs. Flow-through  
organizationofsignalpins simplifies layout.Allinputs are designedwith  
hysteresis forimprovednoise margin.  
Extended commercial range of -40°C to +85°C  
VCC = 5V ±10%  
Balanced Output Drivers:  
±24mA (commercial)  
±16mA (military)  
Reduced system switching noise  
Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, TA =  
25°C  
The FCT162543T/AT/CT/EThave balancedoutputdrive withcurrent  
limitingresistors. Thisofferslowgroundbounce,minimalundershoot,and  
controlledoutputfalltimes–reducingtheneedforexternalseries terminat-  
ingresistors. The FCT162543T/AT/CT/ETare plug-inreplacements for  
the FCT16543T/AT/CT/ETand54/74ABT16543foron-boardbus inter-  
faceapplications.  
FUNCTIONALBLOCKDIAGRAM  
56  
29  
2OEBA  
1OEBA  
1CEBA  
31  
54  
2CEBA  
30  
28  
55  
1
2LEBA  
2OEAB  
1LEBA  
1OEAB  
26  
27  
3
2
2CEAB  
2LEAB  
1CEAB  
1LEAB  
C
D
C
D
15  
5
2A1  
1A1  
42  
52  
2B1  
1B1  
C
D
C
D
TO SEVEN OTHER CHANNELS  
TO SEVEN OTHER CHANNELS  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AUGUST 1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-5445/-  

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