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IDT74FCT16260ATPAG PDF预览

IDT74FCT16260ATPAG

更新时间： 2024-10-28 13:08:43
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
8页 136K
描述
Bus Exchanger, FCT Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, TSSOP-56

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中文翻译

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IDT74FCT16260ATPAG 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP-56针数：56
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.68Is Samacsys：N
其他特性：POWER OFF DISABLE O/PS; IOH MAX DURATION < 1S; MAX OUTPUT SKEW = 0.5NS系列：FCT
JESD-30 代码：R-PDSO-G56JESD-609代码：e3
长度：14 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS EXCHANGER湿度敏感等级：1
位数：12功能数量：1
端口数量：3端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：5.2 ns
认证状态：Not Qualified座面最大高度：1.1 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：6.1 mm
Base Number Matches：1

IDT74FCT16260ATPAG 数据手册

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IDT54/74FCT16260AT/CT/ET  
IDT54/74FCT162260AT/CT/ET  
FAST CMOS  
12-BIT TRI-PORT  
BUS EXCHANGER  
Integrated Device Technology, Inc.  
FEATURES:  
• Common features:  
– 0.5 MICRON CMOS Technology  
– High-speed, low-power CMOS replacement for  
ABT functions  
– Typical tSK(o) (Output Skew) < 250ps  
– Low input and output leakage ≤1µA (max.)  
– ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
– Packages include 25 mil pitch SSOP, 19.6 mil pitch  
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack  
– Extended commercial range of -40°C to +85°C  
– VCC = 5V ±10%  
• Features for FCT16260AT/CT/ET:  
– High drive outputs (-32mA IOH, 64mA IOL)  
– Power off disable outputs permit “live insertion”  
– Typical VOLP (Output Ground Bounce) < 1.0V at  
VCC = 5V, TA = 25°C  
DESCRIPTION:  
The FCT16260AT/CT/ET and the FCT162260AT/CT/ET  
Tri-Port Bus Exchangers are high-speed 12-bit latched bus  
multiplexers/transceivers for use in high-speed microproces-  
sor applications. These Bus Exchangers support memory  
interleaving with latched outputs on the B ports and address  
multiplexing with latched inputs on the B ports.  
The Tri-Port Bus Exchanger has three 12-bit ports. Data  
may be transferred between the A port and either/both of the  
B ports. The latch enable (LE1B, LE2B, LEA1B and LEA2B)  
inputs control data storage. When a latch-enable input is  
HIGH, the latch is transparent. When a latch-enable input is  
LOW, the data at the input is latched and remains latched until  
the latch enable input is returned HIGH. Independent output  
enables (OE1B and OE2B) allow reading from one port while  
writing to the other port.  
The FCT16260AT/CT/ET are ideally suited for driving high  
capacitance loads and low impedance backplanes. The  
output buffers are designed with power off disable capability  
to allow "live insertion" of boards when used as backplane  
drivers.  
• Features for FCT162260AT/CT/ET:  
– Balanced Output Drivers: ±24mA (commercial),  
±16mA (military)  
The FCT162260AT/CT/ET have balanced output drive  
with current limiting resistors. This offers low ground bounce,  
minimal undershoot, and controlled output fall times - reduc-  
ing the need for external series terminating resistors.  
– Reduced system switching noise  
– Typical VOLP (Output Ground Bounce) < 0.6V at  
VCC = 5V,TA = 25°C  
FUNCTIONAL BLOCK DIAGRAM  
OE1B  
LEA1B  
A-1B  
LATCH  
1B1:12  
12  
LE1B  
12  
1B-A  
LATCH  
12  
12  
SEL  
OEA  
1
0
M
U
X
A1:12  
12  
12  
12  
2B-A  
LATCH  
LE2B  
12  
A-2B  
LATCH  
2B1:12  
LEA2B  
OE2B  
12  
3032 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AUGUST 1996  
1996 Integrated Device Technology, Inc.  
5.4  
DSC-3032/6  
1
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