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IDT74FCT138CL PDF预览

IDT74FCT138CL

更新时间: 2024-11-05 22:34:35
品牌 Logo 应用领域
艾迪悌 - IDT 解码器驱动器逻辑集成电路输入元件
页数 文件大小 规格书
6页 70K
描述
FAST CMOS 1-OF-8 DECODER WITH ENABLE

IDT74FCT138CL 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCN, LCC20,.35SQ
针数:20Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.26Is Samacsys:N
其他特性:3 ENABLE INPUTS系列:FCT
JESD-30 代码:S-CQCC-N20JESD-609代码:e0
长度:8.89 mm负载电容(CL):50 pF
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.048 A
功能数量:1端子数量:20
最高工作温度:70 °C最低工作温度:
输出极性:INVERTED封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC20,.35SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:5.1 ns传播延迟(tpd):5.1 ns
认证状态:Not Qualified座面最大高度:2.54 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.89 mmBase Number Matches:1

IDT74FCT138CL 数据手册

 浏览型号IDT74FCT138CL的Datasheet PDF文件第2页浏览型号IDT74FCT138CL的Datasheet PDF文件第3页浏览型号IDT74FCT138CL的Datasheet PDF文件第4页浏览型号IDT74FCT138CL的Datasheet PDF文件第5页浏览型号IDT74FCT138CL的Datasheet PDF文件第6页 
IDT54/74FCT138  
IDT54/74FCT138A  
IDT54/74FCT138C  
FAST CMOS  
1-OF-8 DECODER  
WITH ENABLE  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
• IDT54/74FCT138 equivalent to FAST speed  
IDT54/74FCT138A 35% faster than FAST  
IDT54/74FCT138C 40% faster than FAST  
• Equivalent to FAST speeds output drive over full tem-  
perature and voltage supply extremes  
• IOL = 48mA (commercial) and 32mA (military)  
• CMOS power levels (1mW typ. static)  
• TTL input and output level compatible  
• CMOS output level compatible  
The IDT54/74FCT138/A/C are 1-of-8 decoders built using  
an advanced dual metal CMOS technology. The IDT54/  
74FCT138/A/C accept three binary weighted inputs (A0, A1,  
A2) and, when enabled, provide eight mutually exclusive  
active LOW outputs (O0 - O7). The IDT54/74FCT138/A/C  
feature three enable inputs, two active LOW (E1, E2) and one  
active HIGH (E3). All outputs will be HIGH unless E1 and E2  
are LOW and E3 is HIGH. This multiple enable function allows  
easy parallel expansion of the device to a 1-of-32 (5 lines to  
32 lines) decoder with just four IDT54/74FCT138/A/C devices  
and one inverter.  
• Substantially lower input current levels than FAST  
(5µA max.)  
• JEDEC standard pinout for DIP and LCC  
• Product available in Radiation Tolerant and Radiation  
Enhanced versions  
• Military product compliant to MIL-STD-883, Class B  
• Standard Military Drawing # 5962-87654 is listed on this  
function. Refer to section 2.  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATIONS  
A2  
A1  
A0  
E3  
E1 E2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
A
A
A
E
0
1
2
1
Vcc  
O
O
0
P16-1,  
D16-1,  
SO16-1  
&
1
O2  
O3  
O4  
2
3
7
E
E
O
E16-1  
O
5
O6  
GND  
DIP/SOIC/CERPACK  
TOP VIEW  
INDEX  
3
2
20 19  
18  
4
5
6
7
8
A2  
E1  
NC  
O1  
O2  
NC  
1
17  
16  
15  
14  
L20-2  
2
O3  
O4  
E
O7  
O6  
O5  
O4  
O3  
O2  
O1  
O0  
E3  
10 11 12 13  
9
2581 drw 02  
2581 drw 01  
LCC  
TOP VIEW  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
FAST is a trademark of National Semiconductor Co.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
MAY 1992  
1992 Integrated Device Technology, Inc.  
7.3  
DSC-4625/3  
1

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