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IDT74AUC16374BVI8 PDF预览

IDT74AUC16374BVI8

更新时间: 2024-11-11 14:42:47
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路触发器
页数 文件大小 规格书
8页 88K
描述
Bus Driver, AUC Series, 2-Func, 8-Bit, True Output, CMOS, PBGA56, VFBGA-56

IDT74AUC16374BVI8 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA56,6X10,25
针数:56Reach Compliance Code:not_compliant
风险等级:5.92Is Samacsys:N
系列:AUCJESD-30 代码:R-PBGA-B56
JESD-609代码:e0长度:7 mm
负载电容(CL):15 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:250000000 Hz最大I(ol):0.0001 A
位数:8功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA56,6X10,25封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:0.8/2.7 V
Prop。Delay @ Nom-Sup:4.5 ns传播延迟(tpd):4.5 ns
认证状态:Not Qualified座面最大高度:1.05 mm
子类别:FF/Latches最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):0.8 V标称供电电压 (Vsup):1.2 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:0.65 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:4.5 mm
Base Number Matches:1

IDT74AUC16374BVI8 数据手册

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1.8V CMOS 16-BIT EDGE-  
IDT74AUC16374  
TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
DESCRIPTION:  
FEATURES:  
This 16-bit edge-triggered D-type flip-flop is built using advanced CMOS  
technology. The AUC16374 is particularly suitable for implementing buffer  
registers,I/Oports,bidirectionalbusdrivers,andworkingregisters. Itcanbe  
usedastwo8-bitflip-flopsorone16-bitflip-flop. Onthepositivetransitionofthe  
clock(CLK)input,theQoutputsoftheflip-floptakeonthelogiclevelsatthedata  
(D)inputs.  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• 1.8VOptimized  
• 0.8V to 2.7V Operating Range  
• Inputs/outputs tolerant up to 3.6V  
• Output drivers: ±9mA @ 2.3V  
OEcanbeusedtoplacetheeightoutputsineitheranormallogicstate(high  
orlowlogiclevels)orahigh-impedancestate. Inthehigh-impedancestate,the  
outputsneitherloadnordrivethebuslinessignificantly. Thehigh-impedance  
state and the increased drive provide the capability to drive bus lines without  
needforinterfaceorpullupcomponents. OE doesnotaffecttheinternaloperation  
oftheflip-flop. Olddatacanberetainedornewdatacanbeenteredwhilethe  
outputsareinthehigh-impedancestate.  
• Supports hot insertion  
• Available in TSSOP, TVSOP, and VFBGA packages  
APPLICATIONS:  
• high performance, low voltage communications systems  
• high performance, low voltage computing systems  
Thisdeviceisfullyspecifiedforpartialpower-downapplicationsusingIOFF.  
TheIOFF circuitrydisablestheoutputs,preventingdamagingcurrentbackflow  
through the device when it is powered down.  
To ensure the high-impedance state during power up or power down, OE  
shouldbetiedtoVDD throughapull-upresistor;theminimumvalueoftheresistor  
isdeterminedbythecurrent-sinkingcapabilityofthedriver.  
FUNCTIONALBLOCKDIAGRAM  
1OE  
2OE  
1CLK  
2CLK  
C1  
C1  
1Q1  
2Q1  
1D1  
2D1  
1D  
1D  
TO SEVEN OTHER CHANNELS  
TO SEVEN OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JANUARY 2003  
1
© 2003 Integrated Device Technology, Inc.  
DSC-6179/5  

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