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IDT74ALVCHR16501PA PDF预览

IDT74ALVCHR16501PA

更新时间: 2024-11-09 04:58:31
品牌 Logo 应用领域
艾迪悌 - IDT 总线收发器输出元件
页数 文件大小 规格书
7页 70K
描述
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD

IDT74ALVCHR16501PA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP56,.3,20
针数:56Reach Compliance Code:not_compliant
风险等级:5.92其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:14 mm
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER最大I(ol):0.012 A
湿度敏感等级:1位数:18
功能数量:1端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP56,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:4.5 ns传播延迟(tpd):6.3 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE
宽度:6.1 mmBase Number Matches:1

IDT74ALVCHR16501PA 数据手册

 浏览型号IDT74ALVCHR16501PA的Datasheet PDF文件第2页浏览型号IDT74ALVCHR16501PA的Datasheet PDF文件第3页浏览型号IDT74ALVCHR16501PA的Datasheet PDF文件第4页浏览型号IDT74ALVCHR16501PA的Datasheet PDF文件第5页浏览型号IDT74ALVCHR16501PA的Datasheet PDF文件第6页浏览型号IDT74ALVCHR16501PA的Datasheet PDF文件第7页 
3.3V CMOS 18-BIT UNIVERSAL IDT74ALVCHR16501  
BUS TRANSCEIVER WITH  
3-STATE OUTPUTS  
AND BUS-HOLD  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
• Typical tSK(o) (Output Skew) < 250ps  
This 18-bit universal bus transceiver is built using advanced dual metal  
CMOStechnology.Dataflowineachdirectioniscontrolledbyoutput-enable  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ± 0.3V, Normal Range  
• VCC = 2.7V to 3.6V, Extended Range  
• VCC = 2.5V ± 0.2V  
• CMOS power levels (0.4µ W typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• Available in TSSOP package  
(OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and  
CLKBA) inputs. For A-to-B data flow, the device operates in the transparent  
modewhenLEABishigh. WhenLEABislow, theAdataislatchedifCLKAB  
isheldatahighorlowlogiclevel.IfLEABislow,theAdataisstoredinthelatch/  
flip-floponthelow-to-hightransitionofCLKAB.WhenOEABishigh,theoutputs  
areactive.WhenOEABislow,theoutputsareinthehigh-impedancestate.Data  
flowfromBtoAissimiliartothatofAtoBbutusesOEBA,LEBA,andCLKBA.  
Theoutputenablesarecomplementary(OEABisactivehighandOEBAisactive  
low).  
DRIVE FEATURES:  
• Balanced Output Drivers: ±12mA  
• Low Switching Noise  
TheALVCHR16501hasseriesresistorsinthedeviceoutputstructurewhich  
willsignificantlyreducereducelinenoisewhenusedwithlightloads.Thisdriver  
hasbeendesignedtodrive±12mAatthedesignatedthresholdlevels.  
The ALVCHR16501 has “bus-hold” which retains the inputs’ last state  
whenevertheinputbusgoestoahighimpedance.Thispreventsfloatinginputs  
andeliminatestheneedforpull-up/downresistors.  
APPLICATIONS:  
• 3.3V high speed systems  
• 3.3V and lower voltage computing systems  
FUNCTIONALBLOCKDIAGRAM  
1
OEAB  
55  
CLKAB  
2
LEAB  
28  
LEBA  
30  
CLKBA  
27  
OEBA  
3
1D  
A1  
54  
B1  
C1  
CLK  
1D  
C1  
CLK  
TO 17 OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JANUARY 2004  
1
© 2004 Integrated Device Technology, Inc.  
DSC-4613/2  

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