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IDT72V7260L10BBG PDF预览

IDT72V7260L10BBG

更新时间: 2024-11-16 20:49:55
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
42页 444K
描述
FIFO, 4KX72, 6.5ns, Synchronous, CMOS, PBGA256, PLASTIC, FBGA-256

IDT72V7260L10BBG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:PLASTIC, FBGA-256针数:256
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.84
最长访问时间:6.5 ns其他特性:RETRANSMIT
周期时间:10 nsJESD-30 代码:S-PBGA-B256
JESD-609代码:e1长度:17 mm
内存密度:294912 bit内存宽度:72
湿度敏感等级:3功能数量:1
端子数量:256字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX72可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:3.5 mm
最大供电电压 (Vsup):3.45 V最小供电电压 (Vsup):3.15 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:17 mm
Base Number Matches:1

IDT72V7260L10BBG 数据手册

 浏览型号IDT72V7260L10BBG的Datasheet PDF文件第2页浏览型号IDT72V7260L10BBG的Datasheet PDF文件第3页浏览型号IDT72V7260L10BBG的Datasheet PDF文件第4页浏览型号IDT72V7260L10BBG的Datasheet PDF文件第5页浏览型号IDT72V7260L10BBG的Datasheet PDF文件第6页浏览型号IDT72V7260L10BBG的Datasheet PDF文件第7页 
3.3 VOLTHIGH-DENSITYSUPERSYNCII72-BITFIFO  
512 x 72, 1,024 x 72  
2,048 x 72, 4,096 x 72  
8,192 x 72, 16,384 x 72  
32,768 x 72, 65,536 x 72  
IDT72V7230, IDT72V7240  
IDT72V7250, IDT72V7260  
IDT72V7270, IDT72V7280  
IDT72V7290,IDT72V72100  
Master Reset clears entire FIFO  
FEATURES:  
Partial Reset clears data, but retains programmable settings  
Choose among the following memory organizations:  
Empty, Full and Half-Full flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of eight preselected offsets  
Selectable synchronous/asynchronous timing modes for Almost-  
Empty and Almost-Full flags  
Program programmable flags by either serial or parallel means  
Select IDT Standard timing (using EF and FF flags) or First Word  
Fall Through timing (using OR and IR flags)  
IDT72V7230  
IDT72V7240  
IDT72V7250  
IDT72V7260  
IDT72V7270  
IDT72V7280  
IDT72V7290  
512 x 72  
1,024 x 72  
2,048 x 72  
4,096 x 72  
8,192 x 72  
16,384 x 72  
32,768 x 72  
IDT72V72100 65,536 x 72  
100 MHz operation (10 ns read/write cycle time)  
User selectable input and output port bus-sizing  
- x72 in to x72 out  
- x72 in to x36 out  
- x72 in to x18 out  
Output enable puts data outputs into high impedance state  
Easily expandable in depth and width  
Independent Read and Write Clocks (permit reading and writing  
simultaneously)  
Asynchronous operation of Output Enable, OE  
Read Chip Select ( RCS ) on Read Side  
- x36 in to x72 out  
- x18 in to x72 out  
Available in a 256-pin Fine Pitch Ball Grid Array package (PBGA)  
Features JTAG (Boundary Scan)  
Big-Endian/Little-Endian user selectable word representation  
Fixed, low first word latency  
High-performance submicron CMOS technology  
Industrial temperature range (–40°C to +85°C) is available  
Zero latency retransmit  
Auto power down minimizes standby power consumption  
FUNCTIONALBLOCKDIAGRAM  
D0 -Dn (x72, x36 or x18)  
LD SEN  
SCLK  
WEN  
WCLK  
INPUT REGISTER  
OFFSET REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
RAM ARRAY  
512 x 72  
HF  
FWFT/SI  
PFM  
1,024 x 72  
2,048 x 72  
4,096 x 72  
8,192 x 72  
16,384 x 72  
32,768 x 72  
65,536 x 72  
FSEL0  
FSEL1  
WRITE POINTER  
READ POINTER  
BE  
CONTROL  
LOGIC  
IP  
READ  
CONTROL  
LOGIC  
RT  
BM  
IW  
OW  
BUS  
OUTPUT REGISTER  
RM  
CONFIGURATION  
MRS  
PRS  
RESET  
LOGIC  
RCLK  
TCK  
TRST  
TMS  
TDO  
TDI  
REN  
RCS  
JTAG  
CONTROL  
(BOUNDARY SCAN)  
OE  
4680 drw01  
Q0 -Qn (x72, x36 or x18)  
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.  
DECEMBER 2003  
COMMERCIAL TEMPERATURE RANGE  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4680/10  

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