Datasheet > IDT72V72100

IDT72V72100

更新时间： 2024-02-21 15:01:03

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
42页	437K
描述
3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO

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中文翻译

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数据手册

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IDT72V72100 数据手册

3.3 VOLTHIGH-DENSITYSUPERSYNCII™72-BITFIFO

512 x 72, 1,024 x 72

2,048 x 72, 4,096 x 72

8,192 x 72, 16,384 x 72

32,768 x 72, 65,536 x 72

IDT72V7230, IDT72V7240

IDT72V7250, IDT72V7260

IDT72V7270, IDT72V7280

IDT72V7290,IDT72V72100

• Master Reset clears entire FIFO

FEATURES:

•

Partial Reset clears data, but retains programmable settings

• Choose among the following memory organizations:

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of eight preselected offsets

• Selectable synchronous/asynchronous timing modes for Almost-

Empty and Almost-Full flags

• Program programmable flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or First Word

Fall Through timing (using OR and IR flags)

IDT72V7230

IDT72V7240

IDT72V7250

IDT72V7260

IDT72V7270

IDT72V7280

IDT72V7290



512 x 72

1,024 x 72

2,048 x 72

4,096 x 72

8,192 x 72

16,384 x 72

32,768 x 72

IDT72V72100  65,536 x 72

• 100 MHz operation (10 ns read/write cycle time)

• User selectable input and output port bus-sizing

- x72 in to x72 out

- x72 in to x36 out

- x72 in to x18 out

•

Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• Independent Read and Write Clocks (permit reading and writing

simultaneously)

• Asynchronous operation of Output Enable, OE

• Read Chip Select ( RCS ) on Read Side

- x36 in to x72 out

- x18 in to x72 out

• Available in a 256-pin Fine Pitch Ball Grid Array package (PBGA)

• Features JTAG (Boundary Scan)

•

Big-Endian/Little-Endian user selectable word representation

• Fixed, low first word latency

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

• Zero latency retransmit

• Auto power down minimizes standby power consumption

FUNCTIONALBLOCKDIAGRAM

D0 -Dn (x72, x36 or x18)

LD SEN

SCLK

WEN

WCLK

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

EF/OR

PAE

FLAG

LOGIC

WRITE CONTROL

LOGIC

RAM ARRAY

512 x 72

FWFT/SI

PFM

1,024 x 72

2,048 x 72

4,096 x 72

8,192 x 72

16,384 x 72

32,768 x 72

65,536 x 72

FSEL0

FSEL1

WRITE POINTER

READ POINTER

CONTROL

LOGIC

READ

CONTROL

LOGIC

BUS

OUTPUT REGISTER

CONFIGURATION

MRS

PRS

RESET

LOGIC

RCLK

TCK

TRST

TMS

TDO

TDI

REN

RCS

JTAG

CONTROL

(BOUNDARY SCAN)

4680 drw01

Q0 -Qn (x72, x36 or x18)

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.

DECEMBER 2003

COMMERCIAL TEMPERATURE RANGE

DSC-4680/9

12 3 4 5 6 7...42

中文翻译

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与IDT72V72100相关器件

型号	品牌	获取价格	描述	数据表
IDT72V72100L	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO
IDT72V72100L10	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO
IDT72V72100L10BB	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO
IDT72V72100L10BBG	IDT	获取价格	FIFO, 64KX72, 6.5ns, Synchronous, CMOS, PBGA256, PLASTIC, FBGA-256
IDT72V72100L15	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO
IDT72V72100L15BB	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO
IDT72V72100L15BBG	IDT	获取价格	暂无描述
IDT72V7230	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO
IDT72V7230L	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO
IDT72V7230L10	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO

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