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IDT72V3662L15PFG PDF预览

IDT72V3662L15PFG

更新时间: 2024-11-25 19:36:35
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
30页 322K
描述
FIFO, 4KX36, 10ns, Synchronous, CMOS, PQFP120, GREEN, TQFP-120

IDT72V3662L15PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:GREEN, TQFP-120针数:120
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.84
最长访问时间:10 ns其他特性:MAIL BOX BYPASS REGISTER
周期时间:15 nsJESD-30 代码:S-PQFP-G120
JESD-609代码:e3长度:14 mm
内存密度:147456 bit内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:120字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.4 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

IDT72V3662L15PFG 数据手册

 浏览型号IDT72V3662L15PFG的Datasheet PDF文件第2页浏览型号IDT72V3662L15PFG的Datasheet PDF文件第3页浏览型号IDT72V3662L15PFG的Datasheet PDF文件第4页浏览型号IDT72V3662L15PFG的Datasheet PDF文件第5页浏览型号IDT72V3662L15PFG的Datasheet PDF文件第6页浏览型号IDT72V3662L15PFG的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncBiFIFOTM  
2,048 x 36 x 2  
4,096 x 36 x 2  
IDT72V3652  
IDT72V3662  
IDT72V3672  
8,192 x 36 x 2  
Select IDT Standard timing (using EFA, EFB, FFA and FFB flags  
functions) or First Word Fall Through timing (using ORA, ORB, IRA  
and IRB flag functions)  
Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving  
120-pin Thin Quad Flatpack (TQFP)  
Pin and functionally compatible versions of the 5V operating  
IDT723652/723662/723672  
Pin compatible to the lower density parts, IDT72V3622/72V3632/  
72V3642  
FEATURES  
Memory storage capacity:  
IDT72V3652  
IDT72V3662  
IDT72V3672  
2,048 x 36 x 2  
4,096 x 36 x 2  
8,192 x 36 x 2  
Supports clock frequencies up to 100MHz  
Fast access times of 6.5ns  
Free-running CLKA and CLKB may be asynchronous or coincident  
(simultaneous reading and writing of data on a single clock edge  
is permitted)  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
Two independent clocked FIFOs buffering data in opposite direc-  
tions  
DESCRIPTION  
Mailbox bypass register for each FIFO  
Programmable Almost-Full and Almost-Empty flags  
Microprocessor Interface Control Logic  
FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA  
FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB  
TheIDT72V3652/72V3662/72V3672arepinand functionallycompatible  
versionsoftheIDT723652/723662/723672,designedtorunoffa3.3Vsupply  
forexceptionallylow-powerconsumption. Thesedevicesaremonolithic,high-  
speed,low-power,CMOSBidirectionalSyncFIFO(clocked)memorieswhich  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
Port-A  
Control  
Logic  
W/RA  
RAM  
ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
ENA  
MBA  
36  
FIFO1,  
Mail1  
Reset  
Logic  
RST1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
AEB  
FFA/IRA  
AFA  
FIFO 1  
FS  
0
1
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
FS  
A
0
- A35  
13  
B0 - B35  
FIFO 2  
Status Flag  
EFA/ORA  
FFB/IRB  
AFB  
Logic  
AEA  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
RST2  
RAM  
ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
CLKB  
CSB  
Port-B  
Control  
Logic  
W/RB  
ENB  
Mail 2  
Register  
MBB  
4660 drw01  
MBF2  
CIDTOandMtheMIDTElogRoaCrereIgAisteLredtrTadeEmaMrkoPfInEtegRrateAdDTevUiceTRecEhnologRy,IAnc.NSynGcBEiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
JUNE 2005  
1
2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4660/4  

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