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IDT72V245L10PFI PDF预览

IDT72V245L10PFI

更新时间: 2024-02-17 02:39:14
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
25页 216K
描述
3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18

IDT72V245L10PFI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:QFP, QFP64,.47SQ,20针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.23
最长访问时间:6.5 ns其他特性:EASILY EXPANDABLE IN DEPTH AND WIDTH
最大时钟频率 (fCLK):100 MHz周期时间:10 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
长度:10 mm内存密度:73728 bit
内存集成电路类型:OTHER FIFO内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:64字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX18可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.005 A子类别:FIFOs
最大压摆率:0.03 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mmBase Number Matches:1

IDT72V245L10PFI 数据手册

 浏览型号IDT72V245L10PFI的Datasheet PDF文件第19页浏览型号IDT72V245L10PFI的Datasheet PDF文件第20页浏览型号IDT72V245L10PFI的Datasheet PDF文件第21页浏览型号IDT72V245L10PFI的Datasheet PDF文件第22页浏览型号IDT72V245L10PFI的Datasheet PDF文件第24页浏览型号IDT72V245L10PFI的Datasheet PDF文件第25页 
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM  
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE  
(WITH PROGRAMMABLE FLAGS)  
These devices can easily be adapted to applications requiring more than  
256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth  
Expansion using three IDT72V205/72V215/72V225/72V235/72V245s.  
Maximumdepthislimitedonlybysignalloading.  
Followthesesteps:  
1. The first device must be designated by grounding the First Load (FL)  
control input.  
4.The Read Expansion Out (RXO) pin of each device must be tied to the  
Read Expansion In (RXI) pin of the next device. See Figure 30.  
5.All Load (LD) pins are tied together.  
6.The Half-Full Flag (HF) is not available in this Depth Expansion  
Configuration.  
7.EF, FF, PAE, and PAF are created with composite flags by ORing  
togethereveryrespectiveflags formonitoring.ThecompositePAE  
and PAF flags are not precise.  
8.InDaisyChainmode,theflagoutputsaresingleregister-bufferedand  
thepartialflagsareinasynchronoustimingmode.  
2. Allotherdevices musthave FL inthe HIGHstate.  
3. TheWriteExpansionOut(WXO)pinofeachdevicemustbetiedto  
the Write Expansion In (WXI) pin of the next device. See Figure 30.  
WXO RXO  
WCLK  
WEN  
RS  
RCLK  
REN  
OE  
LD  
IDT  
72V205  
72V215  
72V225  
72V235  
72V245  
Dn  
Qn  
Vcc  
FL  
FF/IR  
EF/OR  
PAF  
PAE  
WXI RXI  
WXO RXO  
WCLK  
WEN  
RS  
LD  
RCLK  
REN  
OE  
IDT  
72V205  
72V215  
72V225  
72V235  
72V245  
Dn  
DATA OUT  
DATA IN  
Qn  
Vcc  
FL  
FF/IR  
EF/OR  
PAE  
PAF  
WXI RXI  
RXO  
WXO  
WCLK  
WRITE CLOCK  
WRITE ENABLE  
RESET  
READ CLOCK  
RCLK  
WEN  
REN  
READ ENABLE  
OUTPUT ENABLE  
RS  
OE  
Dn  
Qn  
IDT  
72V205  
72V215  
72V225  
72V235  
72V245  
LD  
LOAD  
EF/OR  
FF/IR  
FF/IR  
EF/OR  
PAE  
PAF  
PAE  
RXI  
PAF  
WXI  
FIRST LOAD (FL)  
4294 drw 30  
Figure 30. Block Diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 Synchronous  
FIFO Memory With Programmable Flags used in Depth Expansion Configuration  
23  

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