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IDT72V245L10PFI PDF预览

IDT72V245L10PFI

更新时间: 2024-02-07 01:55:35
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
25页 216K
描述
3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18

IDT72V245L10PFI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:QFP, QFP64,.47SQ,20针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.23
最长访问时间:6.5 ns其他特性:EASILY EXPANDABLE IN DEPTH AND WIDTH
最大时钟频率 (fCLK):100 MHz周期时间:10 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
长度:10 mm内存密度:73728 bit
内存集成电路类型:OTHER FIFO内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:64字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX18可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.005 A子类别:FIFOs
最大压摆率:0.03 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mmBase Number Matches:1

IDT72V245L10PFI 数据手册

 浏览型号IDT72V245L10PFI的Datasheet PDF文件第16页浏览型号IDT72V245L10PFI的Datasheet PDF文件第17页浏览型号IDT72V245L10PFI的Datasheet PDF文件第18页浏览型号IDT72V245L10PFI的Datasheet PDF文件第20页浏览型号IDT72V245L10PFI的Datasheet PDF文件第21页浏览型号IDT72V245L10PFI的Datasheet PDF文件第22页 
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM  
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
tCLKH  
tCLKL  
WCLK  
tENH  
tENS  
WEN  
PAE  
n words in FIFO(2)  
,
n Words in FIFO(2),  
n + 1 words in FIFO(2)  
n + 2 words in FIFO(3)  
,
n + 1words in FIFO(3)  
n + 1 words in FIFO(3)  
(4)  
t
PAES  
tSKEW2  
t
PAES  
RCLK  
tENH  
tENS  
4294 drw 22  
REN  
NOTES:  
1. n = PAE offset.  
2. For IDT Standard Mode.  
3. For FWFT Mode.  
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge of WCLK  
and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.  
5. PAE is asserted and updated on the rising edge of RCLK only.  
6. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.  
Figure 22. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)  
tCLKH  
tCLKL  
WCLK  
tENS  
tENH  
WEN  
tPAFS  
tPAFS  
D - (m + 1) Words  
in FIFO  
D - (m + 1) Words in FIFO  
PAF  
D - m Words in FIFO  
(3)  
tSKEW2  
RCLK  
tENH  
tENS  
4294 drw 23  
REN  
NOTES:  
1. m = PAF offset.  
2. D = maximum FIFO Depth.  
In IDT Standard Mode: D = 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245.  
In FWFT Mode: D = 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245.  
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK  
and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed an extra WCLK cycle.  
4. PAF is asserted and updated on the rising edge of WCLK only.  
5. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.  
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)  
19  

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