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IDT72V22115JGI PDF预览

IDT72V22115JGI

更新时间: 2024-11-24 07:52:35
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
14页 137K
描述
FIFO, 1KX9, 10ns, Synchronous, CMOS, PQCC32, GREEN, PLASTIC, LCC-32

IDT72V22115JGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFJ
包装说明:QCCJ,针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.2
最长访问时间:10 ns周期时间:15 ns
JESD-30 代码:R-PQCC-J32JESD-609代码:e3
长度:13.9954 mm内存密度:9216 bit
内存宽度:9功能数量:1
端子数量:32字数:1024 words
字数代码:1000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1KX9可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:RECTANGULAR封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:3.55 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:11.4554 mm
Base Number Matches:1

IDT72V22115JGI 数据手册

 浏览型号IDT72V22115JGI的Datasheet PDF文件第2页浏览型号IDT72V22115JGI的Datasheet PDF文件第3页浏览型号IDT72V22115JGI的Datasheet PDF文件第4页浏览型号IDT72V22115JGI的Datasheet PDF文件第5页浏览型号IDT72V22115JGI的Datasheet PDF文件第6页浏览型号IDT72V22115JGI的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncFIFO™  
256 x 9, 512 x 9,  
1,024 x 9, 2,048 x 9,  
IDT72V201, IDT72V211  
IDT72V221, IDT72V231  
IDT72V241, IDT72V251  
4,096 x 9 and 8,192 x 9  
FEATURES:  
are very high-speed, low-power First-In, First-Out (FIFO) memories with  
clockedreadandwritecontrols.Thearchitecture,functionaloperationandpin  
assignments are identical to those of the IDT72201/72211/72221/72231/  
72241/72251,butoperateatapowersupplyvoltage(Vcc)between3.0Vand  
3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-bit  
memoryarray,respectively.TheseFIFOsareapplicableforawidevarietyof  
databufferingneedssuchasgraphics,localareanetworksandinterprocessor  
communication.  
256 x 9-bit organization IDT72V201  
512 x 9-bit organization IDT72V211  
1,024 x 9-bit organization IDT72V221  
2,048 x 9-bit organization IDT72V231  
4,096 x 9-bit organization IDT72V241  
8,192 x 9-bit organization IDT72V251  
10 ns read/write cycle time  
5V input tolerant  
These FIFOs have 9-bit input and output ports. The input port is  
controlled by a free-running clock (WCLK), and two Write Enable pins  
(WEN1,WEN2). DataiswrittenintotheSynchronousFIFOoneveryrising  
clock edge when the Write Enable pins are asserted. The output port is  
Read and Write clocks can be independent  
Dual-Ported zero fall-through time architecture  
Empty and Full Flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags can be set to controlledbyanotherclockpin(RCLK)andtwoReadEnable pins (REN1,  
any depth  
REN2). The Read Clock can be tied to the Write Clock for single clock  
operationorthe twoclocks canrunasynchronous ofone anotherfordual-  
clockoperation. AnOutputEnable pin(OE)is providedonthe readport  
forthree-state controlofthe output.  
The Synchronous FIFOs have twofixedflags, Empty(EF)andFull(FF).  
Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are  
provided for improved system control. The programmable flags default to  
Empty+7andFull-7forPAE andPAF,respectively.Theprogrammableflag  
offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting  
the Load pin (LD).  
Programmable Almost-Empty and Almost-Full flags default to  
Empty+7, and Full-7, respectively  
Output Enable puts output data bus in high-impedance state  
Advanced submicron CMOS technology  
Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin  
plastic Thin Quad FlatPack (TQFP)  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
These FIFOs are fabricated using IDT's high-speed submicron CMOS  
technology.  
DESCRIPTION:  
TheIDT72V201/72V211/72V221/72V231/72V241/72V251SyncFIFOs™  
FUNCTIONAL BLOCK DIAGRAM  
D0 - D8  
WCLK  
WEN1  
WEN2  
LD  
INPUT REGISTER  
OFFSET REGISTER  
EF  
FLAG  
LOGIC  
PAE  
PAF  
FF  
WRITE CONTROL  
LOGIC  
RAM ARRAY  
256 x 9, 512 x 9,  
1,024 x 9, 2,048 x 9,  
4,096 x 9, 8,192 x 9  
READ POINTER  
WRITE POINTER  
READ CONTROL  
LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
RCLK  
REN1  
REN2  
RS  
OE  
4092 drw 01  
Q0 - Q8  
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
FEBRUARY 2006  
1
©2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4092/4  

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