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IDT72V201L10PFG

更新时间： 2024-11-23 13:08:43
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
14页 117K
描述
FIFO, 256X9, 6.5ns, Synchronous, CMOS, PQFP32, GREEN, PLASTIC, TQFP-32

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中文翻译

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IDT72V201L10PFG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LQFP,针数：32
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.43
最长访问时间：6.5 ns周期时间：10 ns
JESD-30 代码：S-PQFP-G32JESD-609代码：e3
长度：7 mm内存密度：2304 bit
内存宽度：9湿度敏感等级：3
功能数量：1端子数量：32
字数：256 words字数代码：256
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256X9
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：7 mmBase Number Matches：1

IDT72V201L10PFG 数据手册

 浏览型号IDT72V201L10PFG的Datasheet PDF文件第2页浏览型号IDT72V201L10PFG的Datasheet PDF文件第3页浏览型号IDT72V201L10PFG的Datasheet PDF文件第4页浏览型号IDT72V201L10PFG的Datasheet PDF文件第5页浏览型号IDT72V201L10PFG的Datasheet PDF文件第6页浏览型号IDT72V201L10PFG的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncFIFO™  
256 x 9, 512 x 9,  
1,024 x 9, 2,048 x 9,  
IDT72V201, IDT72V211  
IDT72V221, IDT72V231  
IDT72V241, IDT72V251  
4,096 x 9 and 8,192 x 9  
FEATURES:  
clockedreadandwritecontrols.Thearchitecture,functionaloperationandpin  
assignments are identical to those of the IDT72201/72211/72221/72231/  
72241/72251,butoperateatapowersupplyvoltage(Vcc)between3.0Vand  
3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-bit  
memoryarray,respectively.TheseFIFOsareapplicableforawidevarietyof  
databufferingneedssuchasgraphics,localareanetworksandinterprocessor  
communication.  
These FIFOs have 9-bit input and output ports. The input port is  
controlled by a free-running clock (WCLK), and two Write Enable pins  
(WEN1,WEN2). DataiswrittenintotheSynchronousFIFOoneveryrising  
clock edge when the Write Enable pins are asserted. The output port is  
controlledbyanotherclockpin(RCLK)andtwoReadEnable pins (REN1,  
• 256 x 9-bit organization IDT72V201  
• 512 x 9-bit organization IDT72V211  
• 1,024 x 9-bit organization IDT72V221  
• 2,048 x 9-bit organization IDT72V231  
• 4,096 x 9-bit organization IDT72V241  
• 8,192 x 9-bit organization IDT72V251  
• 10 ns read/write cycle time  
• 5V input tolerant  
• Read and Write clocks can be independent  
• Dual-Ported zero fall-through time architecture  
• Empty and Full Flags signal FIFO status  
• Programmable Almost-Empty and Almost-Full flags can be set to REN2). The Read Clock can be tied to the Write Clock for single clock  
any depth  
operationorthe twoclocks canrunasynchronous ofone anotherfordual-  
clockoperation. AnOutputEnable pin(OE)is providedonthe readport  
forthree-state controlofthe output.  
• Programmable Almost-Empty and Almost-Full flags default to  
Empty+7, and Full-7, respectively  
• Output Enable puts output data bus in high-impedance state  
• Advanced submicron CMOS technology  
• Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin  
plastic Thin Quad FlatPack (TQFP)  
The Synchronous FIFOs have twofixedflags, Empty(EF)andFull(FF).  
Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are  
provided for improved system control. The programmable flags default to  
Empty+7andFull-7forPAEandPAF,respectively.Theprogrammableflag  
offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting  
the Load pin (LD).  
• Industrial temperature range (–40°C to +85°C) is available  
These FIFOs are fabricated using IDT's high-speed submicron CMOS  
technology.  
DESCRIPTION:  
TheIDT72V201/72V211/72V221/72V231/72V241/72V251SyncFIFOs™  
are very high-speed, low-power First-In, First-Out (FIFO) memories with  
FUNCTIONAL BLOCK DIAGRAM  
D0 - D8  
WCLK  
WEN1  
WEN2  
LD  
INPUT REGISTER  
OFFSET REGISTER  
EF  
FLAG  
LOGIC  
PAE  
PAF  
FF  
WRITE CONTROL  
LOGIC  
RAM ARRAY  
256 x 9, 512 x 9,  
1,024 x 9, 2,048 x 9,  
4,096 x 9, 8,192 x 9  
READ POINTER  
WRITE POINTER  
READ CONTROL  
LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
RCLK  
REN1  
REN2  
RS  
OE  
4092 drw 01  
Q0 - Q8  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
FEBRUARY 2002  
1
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4092/2  
1234567...14

中文翻译

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与IDT72V201L10PFG相关器件

型号 品牌 获取价格 描述 数据表
IDT72V201L10PFI IDT

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 		3.3 VOLT CMOS SyncFIFO⑩ 256 x 9, 512 x 9, 1,0
IDT72V201L15 IDT

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 		3.3 VOLT CMOS SyncFIFO⑩ 256 x 9, 512 x 9, 1,0
IDT72V201L15J IDT

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 		3.3 VOLT CMOS SyncFIFO⑩ 256 x 9, 512 x 9, 1,0
IDT72V201L15JG IDT

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 		暂无描述
IDT72V201L15JGI IDT

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 		FIFO, 256X9, 10ns, Synchronous, CMOS, PQCC32, GREEN, PLASTIC, LCC-32
IDT72V201L15JGI8 IDT

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 		FIFO, 256X9, 10ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32
IDT72V201L15JI IDT

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 		3.3 VOLT CMOS SyncFIFO⑩ 256 x 9, 512 x 9, 1,0
IDT72V201L15PF IDT

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 		3.3 VOLT CMOS SyncFIFO⑩ 256 x 9, 512 x 9, 1,0
IDT72V201L15PF8 IDT

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 		FIFO, 256X9, 10ns, Synchronous, CMOS, PQFP32, PLASTIC, TQFP-32
IDT72V201L15PFG IDT

获取价格

 		FIFO, 256X9, 10ns, Synchronous, CMOS, PQFP32, GREEN, PLASTIC, TQFP-32

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