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IDT72801L10TFG8 PDF预览

IDT72801L10TFG8

更新时间: 2024-02-09 03:27:56
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
16页 211K
描述
FIFO, 256X9, 6.5ns, Synchronous, CMOS, PQFP64, SLIM, TQFP-64

IDT72801L10TFG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP,针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.44
最长访问时间:6.5 ns周期时间:10 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
长度:10 mm内存密度:2304 bit
内存宽度:9功能数量:2
端子数量:64字数:256 words
字数代码:256工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256X9可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:10 mm
Base Number Matches:1

IDT72801L10TFG8 数据手册

 浏览型号IDT72801L10TFG8的Datasheet PDF文件第7页浏览型号IDT72801L10TFG8的Datasheet PDF文件第8页浏览型号IDT72801L10TFG8的Datasheet PDF文件第9页浏览型号IDT72801L10TFG8的Datasheet PDF文件第11页浏览型号IDT72801L10TFG8的Datasheet PDF文件第12页浏览型号IDT72801L10TFG8的Datasheet PDF文件第13页 
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM  
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9  
COMMERCIAL AND INDUSTRIAL  
TEMPERATURERANGES  
tCLK  
tCLKH  
tCLKL  
RCLKA (RCLKB)  
tENS  
tENH  
RENA1, RENA2  
(RENB1, RENB2)  
NO OPERATION  
tREF  
tREF  
EFA (EFB)  
tA  
QA  
(QB  
0
- QA  
8
VALID DATA  
0
- QB8)  
tOLZ  
tOHZ  
tOE  
OEA (OEB)  
(1)  
SKEW1  
t
WCLKA (WCLKB)  
WENA1 (WENB1)  
WENA2 (WENB2)  
3034 drw 07  
NOTE:  
1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time  
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change state until the next RCLKA (RCLKB)  
Figure 6. Read Cycle Timing  
WCLKA (WCLKB)  
tDS  
DA  
(DB  
0
- DA  
8
D1  
D2  
D3  
0
- DB8)  
D0  
(First Valid Write)  
tENS  
WENA1 (WENB1)  
tENS  
WENA2 (WENB2)  
(If Applicable)  
(1)  
tFRL  
tSKEW1  
RCLKA (RCLKB)  
tREF  
EFA (EFB)  
tENS  
RENA1, RENA2  
(RENB1, RENB2)  
tA  
tA  
QA  
(QB  
0
- QA  
8
D0  
D1  
0
- QB8)  
tOLZ  
tOE  
OEA (OEB)  
NOTE:  
3034 drw 08  
1. When tSKEW1 minimum specification, tFRL = tCLK + tSKEW1  
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1V or tCLK + tSKEW1  
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).  
Figure 7. First Data Word Latency Timing  
10  

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