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IDT72423L25TDB PDF预览

IDT72423L25TDB

更新时间： 2024-11-01 20:27:15
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
16页 186K
描述
FIFO, 64X1, 15ns, Synchronous, CMOS, CDIP24, 0.300 INCH, THIN, CERDIP-24

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IDT72423L25TDB 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：DIP包装说明：0.300 INCH, THIN, CERDIP-24
针数：24Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.71
风险等级：5.92Is Samacsys：N
最长访问时间：15 ns最大时钟频率 (fCLK)：40 MHz
周期时间：25 nsJESD-30 代码：R-GDIP-T24
JESD-609代码：e0长度：32.004 mm
内存密度：64 bit内存集成电路类型：OTHER FIFO
内存宽度：1功能数量：1
端子数量：24字数：64 words
字数代码：64工作模式：SYNCHRONOUS
最高工作温度：125 °C最低工作温度：-55 °C
组织：64X1输出特性：3-STATE
可输出：YES封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP24,.3
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：SERIAL电源：5 V
认证状态：Not Qualified筛选级别：38535Q/M;38534H;883B
座面最大高度：5.08 mm最大待机电流：0.1 A
子类别：FIFOs最大压摆率：0.1 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

IDT72423L25TDB 数据手册

 浏览型号IDT72423L25TDB的Datasheet PDF文件第2页浏览型号IDT72423L25TDB的Datasheet PDF文件第3页浏览型号IDT72423L25TDB的Datasheet PDF文件第4页浏览型号IDT72423L25TDB的Datasheet PDF文件第5页浏览型号IDT72423L25TDB的Datasheet PDF文件第6页浏览型号IDT72423L25TDB的Datasheet PDF文件第7页 
PRELIMINARY
CMOS SINGLE BIT SyncFIFO  
64 X 1, 256 x 1, 512 x 1  
IDT72423  
IDT72203  
IDT72213  
Integrated Device Technology, Inc.  
for a wide variety of serial data buffering needs, especially  
telecommunicationsapplicationssuchasnetworks,modems,  
signal processing, and serial interfaces.  
FEATURES:  
• 64 x 1-bit organization (IDT72423)  
• 256 x 1-bit organization (IDT72203)  
Thesesingle-bitFIFOshave1-bitinput(D)andoutputports  
(Q).Theinputportiscontrolledbyafree-runningclock(WCLK),  
and two write enable pins (WEN1, WEN2). Data is written into  
the Synchronous FIFO on every rising clock edge when the  
writeenablepinsareasserted. Theoutputportiscontrolledby  
another clock pin (RCLK) and a read enable pin (REN). The  
read clock can be tied to the write clock for single clock  
operation or the two clocks can run asynchronous of one  
another for dual clock operation. An output enable pin (OE) is  
provided on the read port for three-state control of the output.  
The Synchronous FIFOs have two fixed flags, Empty (EF)  
and Full (FF). Two programmable flags, Almost-Empty (PAE)  
and Almost-Full (PAF), are provided for improved system  
control. TheprogrammableflagsdefaulttoEmpty+7andFull-  
7 for PAE and PAF, respectively. The programmable flag  
offset is loaded via the Program Inputs (P0 - P7), on the rising  
WCLK when the load pin (LD) is asserted.  
• 512 x 1-bit organization (IDT72213)  
• 10 ns read/write cycle time (IDT72423/72203/72213)  
• Independent read and write clock lines  
• Empty and Full flags signal FIFO status  
• Programmable Almost-Empty and Almost-Full flags can  
be programmed to any depth via a dedicated port (Pn).  
These flags default to Empty+7 and Full-7, respectively.  
• Output enable puts output data bus in high impedance  
state  
• Available in 24-pin SOIC, 24-pin plastic DIP (300 mil.),  
and 24-pin ceramic DIP (300 mil.)  
• Military product compliant to MIL-STD-883, Class B  
Advanced submicron CMOS technology  
DESCRIPTION:  
The IDT72423/72203/72213 SyncFIFO are very high-  
speed, low-power First-In, First-Out (FIFO) memories with a  
word width of 1 and clocked read and write controls. The  
IDT72423/72203/72213 have a 64, 256, and 512 x 1-bit  
memory arrays, respectively. These FIFOs are appropriate  
The IDT72423/72203/72213/ are fabricated using IDT’s  
high-speedsubmicronCMOStechnology.Militarygradeprod-  
uct is manufactured in compliance with the latest revision of  
MIL-STD-883, Class B.  
FUNCTIONAL BLOCK DIAGRAM  
D
P0 - P7  
LD  
WCLK  
WEN1  
WEN2  
INPUT REGISTER  
OFFSET REGISTER  
EF  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
PAE  
PAF  
FF  
RAM ARRAY  
64 x 1  
WRITE POINTER  
256 x 1  
READ POINTER  
512 x 1  
READ CONTROL  
LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
RCLK  
REN  
RS  
OE  
3111 drw 01  
Q
The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
MAY 1994  
1995 Integrated Device Technology, Inc  
DSC-2065/-  
5.04  
1
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