Datasheet > 存储 > FIFO> IDT72275L15TFG

IDT72275L15TFG

更新时间： 2024-01-27 11:19:15

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
25页	227K
描述
FIFO, 32KX18, 10ns, Synchronous, CMOS, PQFP64, STQFP-64

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IDT72275L15TFG 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	STQFP-64	针数：	64
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.9
最长访问时间：	10 ns	其他特性：	RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH
最大时钟频率 (fCLK)：	66.7 MHz	周期时间：	15 ns
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e0
长度：	10 mm	内存密度：	589824 bit
内存集成电路类型：	OTHER FIFO	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	64	字数：	32768 words
字数代码：	32000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	32KX18	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP64,.47SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	240	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.02 A	子类别：	FIFOs
最大压摆率：	0.09 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	20
宽度：	10 mm	Base Number Matches：	1

IDT72275L15TFG 数据手册

IDT72275/72285 SUPERSYNC FIFO™

32,768 x 18, 65,536 x 18

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION

Symbol

D0–D17

MRS

Name

Data Inputs

I/O

Description

Data inputs for a 18-bit bus.

Master Reset

MRSinitializes the read and write pointers to zero and sets the output register to

all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT

Standard mode, one of two programmable flag default settings, and serial or

parallel programming of the offset settings.

PRS

Partial Reset

Retransmit

PRS initializes the read and write pointers to zero and sets the output register to

all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming

method (serial or parallel), and programmable flag settings are all retained.

RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets

the EF flag to LOW (OR to HIGH in FWFT mode) temporarily and does not disturb

the write pointer, programming method, existing timing mode or programmable flag

settings. RT is useful to reread data from the first physical location of the FIFO.

FWFT/SI

WCLK

First Word Fall

Through/Serial In

During Master Reset, selects First Word Fall Through or IDT Standard mode.

After Master Reset, this pin functions as a serial input for loading offset registers

Write Clock

When enabled by WEN, the rising edge of WCLK writes data into the FIFO and

offsets into the programmable registers for parallel programming, and when

enabled by SEN, the rising edge of WCLK writes one bit of data into the

programmable register for serial programming.

WEN

Write Enable

Read Clock

WEN enables WCLK for writing data into the FIFO memory and offset registers.

RCLK

When enabled by REN, the rising edge of RCLK reads data from the FIFO

memory and offsets from the programmable registers.

REN

Read Enable

Output Enable

Serial Enable

Load

REN enables RCLK for reading data from the FIFO memory and offset registers.

OE controls the output impedance of Qn.

SEN

SEN enables serial loading of programmable flag offsets.

During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023

and determines the flag offset programming method, serial or parallel. After

Master Reset, this pin enables writing to and reading from the offset registers

Don't Care

This pin must be tied to either VCC or GND and must not toggle after Master

Reset.

FF/IR

Full Flag/

Input Ready

In the IDT Standard mode, the FF function is selected. FF indicates whether or

not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR

indicates whether or not there is space available for writing to the FIFO memory.

EF/OR

PAF

Empty Flag/

Output Ready

In the IDT Standard mode, the EF function is selected. EF indicates whether or

not the FIFO memory is empty. In FWFT mode, the OR function is selected.

OR indicates whether or not there is valid data available at the outputs.

Programmable

Almost-Full Flag

PAF goes LOW if the number of words in the FIFO memory is more than

total word capacity of the FIFO minus the full offset value m, which is stored in the

Full Offset register. There are two possible default values for m: 127 or 1,023.

PAE

Programmable

Almost-Empty Flag

PAE goes LOW if the number of words in the FIFO memory is less than offset n,

whichisstoredintheEmptyOffsetregister. Therearetwopossibledefaultvalues

for n: 127 or 1,023. Other values for n can be programmed into the device.

Half-Full Flag

Data Outputs

Power

HF indicates whether the FIFO memory is more or less than half-full.

Data outputs for an 18-bit bus.

Q0–Q17

VCC

+5 Volt power supply pins.

GND

Ground

Ground pins.

1 2 345 6 7...25

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与IDT72275L15TFG相关器件

型号	品牌	描述	获取价格	数据表
IDT72275L15TFG8	IDT	FIFO, 32KX18, 10ns, Synchronous, CMOS, PQFP64, STQFP-64	获取价格
IDT72275L15TFGI	IDT	FIFO, 32KX18, 10ns, Synchronous, CMOS, PQFP64, STQFP-64	获取价格
IDT72275L15TFGI8	IDT	FIFO, 32KX18, 10ns, Synchronous, CMOS, PQFP64, STQFP-64	获取价格
IDT72275L15TFI	IDT	FIFO, 32KX18, 10ns, Synchronous, CMOS, PQFP64, STQFP-64	获取价格
IDT72275L15TFI8	IDT	FIFO, 32KX18, 10ns, Synchronous, CMOS, PQFP64, STQFP-64	获取价格
IDT72275L15TFI9	IDT	FIFO, 32KX18, 10ns, Synchronous, CMOS, PQFP64, STQFP-64	获取价格

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