Datasheet > IDT72281

IDT72281

更新时间： 2022-12-14 05:26:55

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
26页	270K
描述
CMOS SuperSync FIFO

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中文翻译

获取价格

数据手册

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IDT72281 数据手册

CMOS SuperSync FIFO™

65,536 x 9

131,072 x 9

IDT72281

IDT72291

• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-

pin Slim Thin Quad Flat Pack (STQFP)

• High-performance submicron CMOS technology

• Industrial temperature range (-40°C to +85°C) is available

FEATURES:

• Choose among the following memory organizations:

IDT72281

IDT72291

65,536 x 9

131,072 x 9

• Pin-compatible with the IDT72261LA/72271LA SuperSync FIFOs

• 10ns read/write cycle time (6.5ns access time)

• Fixed, low first word data latency time

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable

settings

• Retransmit operation with fixed, low first word data

latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag

can default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or First

Word Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

DESCRIPTION:

TheIDT72281/72291areexceptionallydeep,highspeed,CMOSFirst-In-

First-Out(FIFO)memorieswithclockedreadandwritecontrols. TheseFIFOs

offernumerousimprovementsoverpreviousSuperSyncFIFOs,includingthe

following:

• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas

been removed. The Frequency Select pin (FS) has been removed, thus

it is no longer necessary to select which of the two clock inputs, RCLK or

WCLK, is runningatthe higherfrequency.

• The period required by the retransmit operation is now fixed and short.

• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan

emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable

clock cycle counting delay associated with the latency period found on

previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)

SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecom-

munications,datacommunicationsandotherapplicationsthatneedtobuffer

largeamountsofdata.

• Independent Read and Write clocks (permit reading and writing

simultaneously)

FUNCTIONALBLOCKDIAGRAM

D0 -D8

WEN

WCLK

SEN

OFFSET REGISTER

INPUT REGISTER

FF/IR

PAF

EF/OR

PAE

FLAG

LOGIC

WRITE CONTROL

LOGIC

FWFT/SI

RAM ARRAY

65,536 x 9

131,072 x 9

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

Q0 -Q8

4675 drw01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

SEPTEMBER 2002



DSC-4675/2

12 3 4 5 6 7...26

中文翻译

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与IDT72281相关器件

型号	品牌	获取价格	描述	数据表
IDT72281L	IDT	获取价格	CMOS SuperSync FIFO
IDT72281L10PF	IDT	获取价格	CMOS SuperSync FIFO
IDT72281L10PF9	IDT	获取价格	FIFO, 64KX9, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
IDT72281L10PFG	IDT	获取价格	FIFO, 64KX9, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
IDT72281L10PFG8	IDT	获取价格	FIFO, 64KX9, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
IDT72281L10PFI	IDT	获取价格	CMOS SuperSync FIFO
IDT72281L10TF	IDT	获取价格	CMOS SuperSync FIFO
IDT72281L10TF8	IDT	获取价格	FIFO, 64KX9, 6.5ns, Synchronous, CMOS, PQFP64, STQFP-64
IDT72281L10TFG	IDT	获取价格	FIFO, 64KX9, 6.5ns, Synchronous, CMOS, PQFP64, STQFP-64
IDT72281L10TFG8	IDT	获取价格	FIFO, 64KX9, 6.5ns, Synchronous, CMOS, PQFP64, STQFP-64

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