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IDT72275L15TF PDF预览

IDT72275L15TF

更新时间： 2024-02-10 22:37:48
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
25页 227K
描述
CMOS SUPERSYNC FIFO⑩

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IDT72275L15TF 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：STQFP-64针数：64
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.9
最长访问时间：10 ns其他特性：RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH
最大时钟频率 (fCLK)：66.7 MHz周期时间：15 ns
JESD-30 代码：S-PQFP-G64JESD-609代码：e0
长度：10 mm内存密度：589824 bit
内存集成电路类型：OTHER FIFO内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：64字数：32768 words
字数代码：32000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：32KX18可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP64,.47SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：5 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.02 A子类别：FIFOs
最大压摆率：0.09 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：20
宽度：10 mmBase Number Matches：1

IDT72275L15TF 数据手册

 浏览型号IDT72275L15TF的Datasheet PDF文件第1页浏览型号IDT72275L15TF的Datasheet PDF文件第2页浏览型号IDT72275L15TF的Datasheet PDF文件第4页浏览型号IDT72275L15TF的Datasheet PDF文件第5页浏览型号IDT72275L15TF的Datasheet PDF文件第6页浏览型号IDT72275L15TF的Datasheet PDF文件第7页 
IDT72275/72285 SUPERSYNC FIFO™  
32,768 x 18, 65,536 x 18  
COMMERCIAL TEMPERATURE RANGE  
DESCRIPTION (Continued)  
outputs of one FIFO are connected to the corresponding data  
inputs of the next). No external logic is required.  
DuringMasterReset(MRS)thefollowingeventsoccur:The  
read and write pointers are set to the first location of the FIFO.  
The FWFT pin selects IDT Standard mode or FWFT mode.  
The LD pin selects either a partial flag default setting of 127  
with parallel programming or a partial flag default setting of  
1,023withserialprogramming. Theflagsareupdatedaccord-  
ing to the timing mode and default offsets selected.  
The Partial Reset (PRS) also sets the read and write  
pointers to the first location of the memory. However, the  
timing mode, partial flag programming method, and default or  
programmed offset settings existing before Partial Reset  
remain unchanged. The flags are updated according to the  
timing mode and offsets in effect. PRS is useful for resetting  
a device in mid-operation, when reprogramming partial flags  
would be undesirable.  
These FIFOs have five flag pins, EF/OR (Empty Flag or  
Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full  
Flag), PAE(Programmable Almost-Empty flag) and PAF(Pro-  
grammable Almost-Full flag). The EF and FF functions are  
selected in IDT Standard mode. The IRand ORfunctions are  
selected in FWFT mode. HF, PAE and PAF are always  
available for use, irrespective of timing mode.  
PAEand PAFcan be programmed independently to switch  
at any point in memory. (See Table I and Table II.) Program-  
mable offsets determine the flag switching threshold and can  
be loaded by two methods: parallel or serial. Two default  
offset settings are also provided, so that PAE can be set to  
switch at 127 or 1,023 locations from the empty boundary and  
thePAFthresholdcanbesetat127or1,023locationsfromthe  
full boundary. These choices are made with the LD pin during  
Master Reset.  
The Retransmit function allows data to be reread from the  
FIFO more than once. A LOW on the RTinput during a rising  
RCLK edge initiates a retransmit operation by setting the read  
pointer to the first location of the memory array.  
If, at any time, the FIFO is not actively performing an  
operation, the chip will automatically power down. Once in the  
power down state, the standby supply current consumption is  
minimized. Initiating any operation (by activating control  
inputs) will immediately take the device out of the power down  
state.  
For serial programming, SEN together with LD on each  
rising edge of WCLK, are used to load the offset registers via  
the Serial Input (SI). For parallel programming, WENtogether  
with LD on each rising edge of WCLK, are used to load the  
offset registers via Dn. REN together with LD on each rising  
edge of RCLK can be used to read the offsets in parallel from  
Qn regardless of whether serial or parallel offset loading has  
been selected.  
The IDT72275/72285 are fabricated using IDT’s high speed  
submicron CMOS technology.  
PARTIAL RESET
)
MASTER RESET
)
READ CLOCK (RCLK)  
WRITE CLOCK (WCLK)  
READ ENABLE 
)
WRITE ENABLE
LOAD
)
OUTPUT ENABLE
)
)
DATA OUT (Q  
RETRANSMIT
EMPTY FLAG/OUTPUT READY
PROGRAMMABLE ALMOST-EMPTY
HALF FULL FLAG
0 - Qn)  
DATA IN (D  
0 - Dn)  
IDT  
72275  
72285  
)
SERIAL ENABL
)
FIRST WORD FALL THROUGH/SERIAL INPUT  
(FWFT/SI)  
)
)
FULL FLAG/INPUT READY )  
)
PROGRAMMABLE ALMOST-FULL
)
4674 drw 03  
Figure 1. Block Diagram of Single 32,768 x 18 and 65,536 x 18 Synchronous FIFO  
3
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