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IDT72240L10TC PDF预览

IDT72240L10TC

更新时间: 2024-11-21 13:08:43
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路光电二极管先进先出芯片时钟
页数 文件大小 规格书
11页 98K
描述
FIFO, 4KX8, 6.5ns, Synchronous, CMOS, CDIP28, 0.300 INCH, THIN, SIDE BRAZED, DIP-28

IDT72240L10TC 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.5
Is Samacsys:N最长访问时间:6.5 ns
周期时间:10 nsJESD-30 代码:R-CDIP-T28
JESD-609代码:e0长度:35.56 mm
内存密度:32768 bit内存宽度:8
功能数量:1端子数量:28
字数:4096 words字数代码:4000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4KX8
可输出:YES封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):225认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:7.62 mmBase Number Matches:1

IDT72240L10TC 数据手册

 浏览型号IDT72240L10TC的Datasheet PDF文件第2页浏览型号IDT72240L10TC的Datasheet PDF文件第3页浏览型号IDT72240L10TC的Datasheet PDF文件第4页浏览型号IDT72240L10TC的Datasheet PDF文件第5页浏览型号IDT72240L10TC的Datasheet PDF文件第6页浏览型号IDT72240L10TC的Datasheet PDF文件第7页 
IDT72420  
IDT72200  
IDT72210  
IDT72220  
IDT72230  
IDT72240  
CMOS SyncFIFO™  
64 x 8, 256 x 8,  
512 x 8, 1,024 x 8,  
2,048 x 8 and 4,096 x 8  
FEATURES:  
DESCRIPTION:  
64 x 8-bit organization (IDT72420)  
TheIDT72420/72200/72210/72220/72230/72240SyncFIFO™arevery  
high-speed, low-power First-In, First-Out (FIFO) memories with clocked  
read and write controls. These devices have a 64, 256, 512, 1,024, 2,048,  
and 4,096 x 8-bit memory array, respectively. These FIFOs are applicable  
for a wide variety of data buffering needs, such as graphics, Local Area  
Networks (LANs), and interprocessor communication.  
256 x 8-bit organization (IDT72200)  
512 x 8-bit organization (IDT72210)  
1,024 x 8-bit organization (IDT72220)  
2,048 x 8-bit organization (IDT72230)  
4,096 x 8-bit organization (IDT72240)  
10 ns read/write cycle time (IDT72420/72200/72210/72220/72230/  
72240)  
Read and Write Clocks can be asynchronous or coincidental  
Dual-Ported zero fall-through time architecture  
Empty and Full flags signal FIFO status  
Almost-Empty and Almost-Full flags set to Empty+7 and Full-7,  
respectively  
Output enable puts output data bus in high-impedance state  
Produced with advanced submicron CMOS technology  
Available in 28-pin 300 mil plastic DIP  
For surface mount product please see the IDT72421/72201/72211/ provided for improved system control. The partial (AE) flags are set to  
72221/72231/72241 data sheet  
These FIFOs have 8-bit input and output ports. The input port is  
controlled by a free-running clock (WCLK), and a Write Enable pin (WEN).  
Data is written into the Synchronous FIFO on every clock when WEN is  
asserted. The output port is controlled by another clock pin (RCLK) and a  
Read Enable pin (REN). The Read Clock can be tied to the Write Clock for  
single clock operation or the two clocks can run asynchronous of one  
another for dual clock operation. An Output Enable pin (OE) is provided on  
the read port for three-state control of the output.  
These Synchronous FIFOs have twoendpointflags, Empty(EF)andFull  
(FF). Two partial flags, Almost-Empty (AE) and Almost-Full (AF), are  
Empty+7 and Full-7 for AE and AF respectively.  
These FIFOs are fabricated using IDTs high-speed submicron CMOS  
technology.  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
FUNCTIONAL BLOCK DIAGRAM  
D0 - D7  
WCLK  
WEN  
INPUT REGISTER  
EF  
AE  
AF  
FF  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
RAM ARRAY  
64 x 8, 256 x 8,  
512 x 8, 1,024 x 8,  
2,048 x 8, 4,096 x 8  
WRITE POINTER  
READ POINTER  
READ CONTROL  
LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
RCLK  
RS  
REN  
OE  
2680 drw01  
Q0 - Q7  
CIDTOandMtheMIDTElogRoarCetrIadAemLarksoTfInEtegMratePdDEevRiceATecThnUologRy,IEnc.ThReSAyncNFIFGOisEatrademarkofIntegratedDeviceTechnology,Inc.  
FEBRUARY 2006  
1
©2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-2680/4  

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