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IDT71V35781YSA183BGI8 PDF预览

IDT71V35781YSA183BGI8

更新时间： 2024-11-09 15:44:43
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
22页 621K
描述
Cache SRAM, 256KX18, 3.3ns, CMOS, PBGA119, BGA-119

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IDT71V35781YSA183BGI8 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：BGA, BGA119,7X17,50
针数：119Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.92Base Number Matches：1

IDT71V35781YSA183BGI8 数据手册

 浏览型号IDT71V35781YSA183BGI8的Datasheet PDF文件第2页浏览型号IDT71V35781YSA183BGI8的Datasheet PDF文件第3页浏览型号IDT71V35781YSA183BGI8的Datasheet PDF文件第4页浏览型号IDT71V35781YSA183BGI8的Datasheet PDF文件第5页浏览型号IDT71V35781YSA183BGI8的Datasheet PDF文件第6页浏览型号IDT71V35781YSA183BGI8的Datasheet PDF文件第7页 
128K x 36, 256K x 18  
IDT71V35761YS  
IDT71V35781YS  
IDT71V35761YSA  
IDT71V35781YSA  
3.3VSynchronousSRAMs  
3.3VI/O,PipelinedOutputs  
BurstCounter,SingleCycleDeselect  
Features  
Description  
◆
128K x 36, 256K x 18 memory configurations  
The IDT71V35761/781 are high-speed SRAMs organized as  
128Kx36/256Kx18.TheIDT71V35761/781SRAMscontainwrite,data,  
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate  
aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof  
thewritecycle.  
◆
Supports high system speed:  
Commercial:  
– 200MHz 3.1ns clock access time  
CommercialandIndustrial:  
– 183MHz 3.3ns clock access time  
– 166MHz 3.5ns clock access time  
LBO input selects interleaved or linear burst mode  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V35761/81canprovidefourcyclesofdata  
forasingleaddress presentedtotheSRAM. Aninternalburstaddress  
◆
◆
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
3.3V I/O  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
◆
◆
◆
◆
Optional - Boundary Scan JTAG Interface (IEEE 1149.1 orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
compliant)  
andthe LBO inputpin.  
◆
Packaged in a JEDEC Standard 100-pin plastic thin quad  
TheIDT71V35761/781SRAMsutilizeIDT’slatesthigh-performance  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
grid array  
100-pin thinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and 165 fine pitch ball grid array.  
PinDescriptionSummary  
A0-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS  
0
, CS  
1
Chip Selects  
Output Enable  
OE  
GW  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
BWE  
BW , BW  
(1)  
1
2
, BW  
3
, BW  
4
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
TMS  
TDI  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
TRST  
ZZ  
Test Clock  
Test Data Output  
Synchronous  
Asynchronous  
Asynchronous  
Synchronous  
N/A  
JTAG Reset (Optional)  
Sleep Mode  
I/O  
0
-I/O31, I/OP1-I/OP4  
DD, VDDQ  
SS  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
Supply  
Supply  
V
N/A  
NOTE:  
6445 tbl 01  
1. BW3 and BW4 are not applicable for the IDT71V35781.  
MAY 2004  
1
©2004 IntegratedDeviceTechnology,Inc.  
DSC-6445/01  
1234567...22

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与IDT71V35781YSA183BGI8相关器件

型号 品牌 获取价格 描述 数据表
IDT71V35781YSA183BQ IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35781YSA183BQI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35781YSA183PF IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35781YSA183PFI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35781YSA200BG IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35781YSA200BG8 IDT

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 		Cache SRAM, 256KX18, 3.1ns, CMOS, PBGA119, BGA-119
IDT71V35781YSA200BGI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35781YSA200BQ IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35781YSA200BQI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin
IDT71V35781YSA200PF IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Sin

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