IDT71V3577S
IDT71V3579S
IDT71V3577SA
IDT71V3579SA
128K X 36, 256K X 18
3.3V Synchronous SRAMs
3.3V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
Description
Features
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The IDT71V3577/79 are high-speed SRAMs organized as
128Kx36/256Kx18.TheIDT71V3577/79SRAMs containwrite,data,
address andcontrolregisters.Therearenoregisters inthedataoutput
path(flow-througharchitecture).InternallogicallowstheSRAMtogen-
erateaself-timedwritebaseduponadecisionwhichcanbeleftuntilthe
endofthe write cycle.
128K x 36, 256K x 18 memory configurations
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Supports fast access times:
Commercial:
– 7.5ns up to 117MHz clock frequency
CommercialandIndustrial:
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
LBO input selects interleaved or linear burst mode
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner,astheIDT71V3577/79canprovidefourcyclesofdata
forasingleaddress presentedtotheSRAM. Aninternalburstaddress
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe
next three rising clock edges. The order of these three addresses are
definedbytheinternalburstcounterandtheLBO inputpin.
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Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
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Packaged in a JEDEC Standard 100-pin plastic thin quad
The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray
(BGA) and a 165 fine pitch ball grid array (fBGA).
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball
grid array
PinDescriptionSummary
A0-A17
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Chip Enable
CE
CS0, CS1
OE
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
GW
BWE
(1)
BW1, BW2, BW3, BW4
CLK
ADV
ADSC
ADSP
LBO
Clock
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
N/A
Synchronous
Synchronous
Synchronous
DC
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
TMS
TDI
Synchronous
Synchronous
N/A
TCK
TDO
Test Clock
Test Data Output
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
JTAG Reset (Optional)
Sleep Mode
TRST
ZZ
I/O0-I/O31, I/OP1-I/OP4
VDD, VDDQ
Data Input / Output
Core Power, I/O Power
Ground
Supply
Supply
VSS
N/A
NOTE:
5280 tbl 01
1. BW3 and BW4 are not applicable for the IDT71V3579.
FEBRUARY 2005
1
©2005IntegratedDeviceTechnology,Inc.
DSC-5280/08