Datasheet > IDT71V3557SA85BGGI8

IDT71V3557SA85BGGI8

更新时间： 2024-11-15 06:15:59

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
28页	997K
描述
Cache SRAM, 128KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, ROHS COMPLIANT, BGA-119

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IDT71V3557SA85BGGI8 数据手册

浏览型号IDT71V3557SA85BGGI8的Datasheet PDF文件第2页

浏览型号IDT71V3557SA85BGGI8的Datasheet PDF文件第3页

浏览型号IDT71V3557SA85BGGI8的Datasheet PDF文件第4页

浏览型号IDT71V3557SA85BGGI8的Datasheet PDF文件第5页

浏览型号IDT71V3557SA85BGGI8的Datasheet PDF文件第6页

浏览型号IDT71V3557SA85BGGI8的Datasheet PDF文件第7页

128K x 36, 256K x 18,

IDT71V3557S

IDT71V3559S

IDT71V3557SA

IDT71V3559SA

3.3V Synchronous ZBT™ SRAMs

3.3V I/O, Burst Counter,

Flow-Through Outputs

Features

it read or write.

◆

128K x 36, 256K x 18 memory configurations

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

The IDT71V3557/59 contain address, data-in and control signal

registers.Theoutputsareflow-through(nooutputdataregister).Output

enable is the only asynchronous signal and can be used to disable the

outputsatanygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V3557/59

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser

todeselectthedevicewhendesired.Ifanyoneofthesethreeisnotasserted

when ADV/LD is low, no new memory operation can be

initiated. However, any pending data transfers (reads or writes) will

be completed. The data bus will tri-state one cycle after chip is de-

selectedorawriteisinitiated.

The IDT71V3557/59 have an on-chip burst counter. In the burst

mode, the IDT71V3557/59 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter

(ADV/LD = HIGH).

◆

ZBT^TMFeature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates

the need to control OE

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW¹- BW⁴) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 3.3V (±5%) I/O Supply (VDDQ)

Optional Boundary Scan JTAG Interface (IEEE 1149.1

complaint)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine

pitch ball grid array (fBGA)

◆

Description

TheIDT71V3557/59are3.3Vhigh-speed4,718,592-bit(4.5Mega-

bit)synchronous SRAMs organizedas 128Kx36/256Kx18. Theyare

designed to eliminate dead bus cycles when turning the bus around

between reads and writes, or writes and reads. Thus they have been

given the name ZBT^TM, or Zero Bus Turnaround.

The IDT71V3557/59 SRAMs utilize IDT's latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pin thinplasticquadflatpack(TQFP)aswellasa119 ballgridarray

(BGA) and a 165 fine pitch ball grid array (fBGA).

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andonthenextclockcycletheassociateddatacycleoccurs,be

PinDescriptionSummary

A0-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE¹, CE2, CE²

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW¹, BW², BW³, BW⁴

CLK

ADV/LD

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

LBO

TMS

Synchronous

N/A

TDI

TCK

Te s t Cl o c k

TDO

Te s t Data Outp ut

Synchronous

Asynchronous

Synchronous

Static

JTAG Reset (Optional)

Sleep Mode

TRST

I/O0-I/O31, I/OP1-I/OP4

VDD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

VSS

Static

52 82 tb l 01

DECEMBER 2005

DSC-5282/08

12 3 4 5 6 7...28

中文翻译

下载PDF

与IDT71V3557SA85BGGI8相关器件

型号	品牌	获取价格	描述	数据表
IDT71V3557SA85BGI	IDT	获取价格	128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out
IDT71V3557SA85BGI8	IDT	获取价格	ZBT SRAM, 128KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, POWER, PLASTIC, BGA-119
IDT71V3557SA85BQ	IDT	获取价格	128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out
IDT71V3557SA85BQG	IDT	获取价格	Cache SRAM, 128KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, ROHS COMPLIANT, FBGA-165
IDT71V3557SA85BQGI	IDT	获取价格	Cache SRAM, 128KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, ROHS COMPLIANT, FBGA-165
IDT71V3557SA85BQI	IDT	获取价格	128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out
IDT71V3557SA85PF	IDT	获取价格	128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out
IDT71V3557SA85PFG	IDT	获取价格	Synchronous ZBT SRAMs
IDT71V3557SA85PFGI	IDT	获取价格	Synchronous ZBT SRAMs
IDT71V3557SA85PFI	IDT	获取价格	128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out

与IDT71V3557SA85BGGI8相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

5
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

2
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

29
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

12

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT71V3557SA85BGGI8

IDT71V3557SA85BGGI8 数据手册

与IDT71V3557SA85BGGI8相关器件

与IDT71V3557SA85BGGI8相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IDT71V3557SA85BGGI8

IDT71V3557SA85BGGI8 数据手册

与IDT71V3557SA85BGGI8相关器件

与IDT71V3557SA85BGGI8相关文章

您还可以找

您在本页遇到什么问题？