Datasheet > IDT71V3556XS

IDT71V3556XS

更新时间： 2024-11-30 00:22:43

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
25页	489K
描述
3.3V Synchronous ZBT SRAMs

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中文翻译

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数据手册

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IDT71V3556XS 数据手册

IDT71V3556S/XS

IDT71V3558S/XS

IDT71V3556SA/XSA

IDT71V3558SA/XSA

128K x 36, 256K x 18

3.3V Synchronous ZBT SRAMs

3.3V I/O, Burst Counter

Pipelined Outputs

Description

Features

◆

TheIDT71V3556/58are3.3Vhigh-speed4,718,592-bit(4.5Mega-

bit) synchronous SRAMS. They are designed to eliminate dead bus

cycles when turning the bus around between reads and writes, or

writes and reads. Thus, they have been given the name ZBT^TM, or

Zero Bus Turnaround.

128K x 36, 256K x 18 memory configurations

◆

Supports high performance system speed - 200 MHz (x18)

(3.2 ns Clock-to-Data Access)

Supports high performance system speed - 166 MHz (x36)

◆

(3.5 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

◆

Address and control signals are applied to the SRAM during one

clock cycle, and two cycles later the associated data cycle occurs, be

it read or write.

cycles

◆

Internally synchronized output buffer enable eliminates the

The IDT71V3556/58 contain data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be

used to disable the outputs at any given time.

need to control OE

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

◆

A Clock Enable (CEN) pin allows operation of the IDT71V3556/58

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

There are three chip enable pins (CE¹, CE2, CE2) that allow the

user to deselect the device when desired. If any one of these three are

not asserted when ADV/LD is low, no new memory operation can be

initiated. However, any pending data transfers (reads or writes) will be

completed.Thedatabuswilltri-statetwocyclesafterchipisdeselected

orawriteisinitiated.

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)

Optional- Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

◆

Pin Description Summary

-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

1, CE

, CE

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

1, BW

, BW

CLK

ADV/LD

LBO

TMS

TDI

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

Synchronous

N/A

TCK

Test Clock

TDO

TRST

Test Data Output

Synchronous

Asynchronous

Synchronous

Static

JTAG Reset (Optional)

Sleep Mode

I/O

0-I/O31, I/OP1-I/OP4

Data Input / Output

Core Power, I/O Power

Ground

DD, VDDQ

Supply

Static

5281 tbl 01

JANUARY 2015

DSC-5281/12

12 3 4 5 6 7...25

中文翻译

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与IDT71V3556XS相关器件

型号	品牌	获取价格	描述	数据表
IDT71V3556XS100BG	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PBGA119
IDT71V3556XS100BG8	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PBGA119
IDT71V3556XS100BGG	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PBGA119, 14 X 22 MM, ROHS COMPLIANT, PLASTIC, MS-028AA, BGA-
IDT71V3556XS100BGG8	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PBGA119
IDT71V3556XS100BGGI	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PBGA119, 14 X 22 MM, ROHS COMPLIANT, PLASTIC, MS-028AA, BGA-
IDT71V3556XS100BGGI8	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PBGA119
IDT71V3556XS100BQ8	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PBGA165
IDT71V3556XS100BQG	IDT	获取价格	3.3V Synchronous ZBT SRAMs
IDT71V3556XS100BQGI	IDT	获取价格	3.3V Synchronous ZBT SRAMs
IDT71V3556XS100BQI8	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PBGA165

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