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IDT71V2546S100PFG

更新时间： 2024-11-16 20:08:43
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
28页 512K
描述
ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-100

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中文翻译

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IDT71V2546S100PFG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.49
最长访问时间：5 ns其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：20 mm内存密度：4718592 bit
内存集成电路类型：ZBT SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：128KX36封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

IDT71V2546S100PFG 数据手册

 浏览型号IDT71V2546S100PFG的Datasheet PDF文件第2页浏览型号IDT71V2546S100PFG的Datasheet PDF文件第3页浏览型号IDT71V2546S100PFG的Datasheet PDF文件第4页浏览型号IDT71V2546S100PFG的Datasheet PDF文件第5页浏览型号IDT71V2546S100PFG的Datasheet PDF文件第6页浏览型号IDT71V2546S100PFG的Datasheet PDF文件第7页 
IDT71V2546S  
IDT71V2548S  
IDT71V2546SA  
IDT71V2548SA  
128K x 36, 256K x 18  
3.3V Synchronous ZBT™ SRAMs  
2.5V I/O, Burst Counter  
Pipelined Outputs  
Features  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitread  
or write.  
◆
128K x 36, 256K x 18 memory configurations  
◆
Supports high performance system speed - 150 MHz  
(3.8 ns Clock-to-Data Access)  
The IDT71V2546/48 contain data I/O, address and control signal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
AClockEnable(CEN)pinallowsoperationoftheIDT71V2546/48to  
besuspendedaslongasnecessary.Allsynchronousinputsareignored  
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
ZBTTM Feature - No dead cycles between write and read  
◆
cycles  
◆
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
◆
◆
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)  
Optional Boundary Scan JTAG Interface (IEEE1149.1  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
to deselect the device when desired. If any one of these three are not  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Thedatabuswilltri-statetwocyclesafterchipisdeselectedorawriteis  
initiated.  
◆
◆
◆
◆
◆
complaint)  
TheIDT71V2546/48hasanon-chipburstcounter.Intheburstmode,  
theIDT71V2546/48canprovidefourcyclesofdataforasingleaddress  
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe  
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst  
sequence. The ADV/LD signal is used to load a new external address  
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =  
HIGH).  
The IDT71V2546/48 SRAMs utilize IDT's latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and 165 fine pitch ball grid array (fBGA).  
◆
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine  
pitch ball grid array  
Description  
TheIDT71V2546/48 are3.3Vhigh-speed4,718,592-bit(4.5Mega-  
bit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbuscycles  
when turning the bus around between reads and writes, or writes and  
reads. Thus, they have been given the name ZBT , or Zero Bus  
Turnaround.  
TM  
PinDescriptionSummary  
0
17  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
1
2
2
CE , CE , CE  
Output Enable  
OE  
R/W  
CEN  
Read/Write Signal  
Clock Enable  
Individual Byte Write Selects  
Clock  
1
2
3
4
BW , BW , BW , BW  
CLK  
ADV/LD  
LBO  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Static  
TMS  
TDI  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
TRST  
ZZ  
Test Clock  
Test Data Output  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Static  
JTAG Reset (Optional)  
Sleep Mode  
0
31  
P1  
P4  
I/O -I/O , I/O -I/O  
Data Input / Output  
Core Power, I/O Power  
Ground  
DD DDQ  
V
, V  
Supply  
Supply  
SS  
V
Static  
5294 tbl 01  
MAY 2002  
1
©2002IntegratedDeviceTechnology,Inc.  
DSC-5294/03  
1234567...28

中文翻译

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与IDT71V2546S100PFG相关器件

型号 品牌 获取价格 描述 数据表
IDT71V2546S100PFI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2546S100PFI8 IDT

获取价格

 		ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQFP
IDT71V2546S100PFI9 IDT

获取价格

 		ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQFP
IDT71V2546S133B IDT

获取价格

 		ZBT SRAM, 128KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119
IDT71V2546S133BG IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2546S133BG8 IDT

获取价格

 		ZBT SRAM, 128KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119
IDT71V2546S133BGI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2546S133BQ IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2546S133BQI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2546S133PF IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

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