Datasheet > IDT71V2546S150B

IDT71V2546S150B

更新时间： 2024-11-17 05:45:03

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
28页	496K
描述
ZBT SRAM, 128KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119

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中文翻译

获取价格

数据手册

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IDT71V2546S150B 数据手册

IDT71V2546S/XS

IDT71V2548S/XS

128K x 36, 256K x 18

3.3V Synchronous ZBT™ SRAMs

IDT71V2546SA/XSA

IDT71V2548SA/XSA

2.5V I/O, Burst Counter

Pipelined Outputs

Features

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle, andtwocycleslatertheassociateddatacycleoccurs, beitread

or write.

◆

128K x 36, 256K x 18 memory configurations

◆

Supports high performance system speed - 150 MHz

(3.8 ns Clock-to-Data Access)

The IDT71V2546/48 contain data I/O, address and control signal

registers.Outputenableistheonlyasynchronoussignalandcanbeused

todisabletheoutputsatanygiventime.

AClockEnable(CEN)pinallowsoperationoftheIDT71V2546/48to

besuspendedaslongasnecessary.Allsynchronousinputsareignored

when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious

values.

◆

ZBT^TMFeature - No dead cycles between write and read

cycles

◆

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

◆

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)

Optional Boundary Scan JTAG Interface (IEEE1149.1

Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser

to deselect the device when desired. If any one of these three are not

assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.

However,anypendingdatatransfers(readsorwrites)willbecompleted.

Thedatabuswilltri-statetwocyclesafterchipisdeselectedorawriteis

initiated.

◆

complaint)

TheIDT71V2546/48hasanon-chipburstcounter.Intheburstmode,

theIDT71V2546/48canprovidefourcyclesofdataforasingleaddress

presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe

LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst

sequence. The ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =

HIGH).

The IDT71V2546/48 SRAMs utilize IDT's latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and 165 fine pitch ball grid array (fBGA).

◆

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine

pitch ball grid array

Description

TheIDT71V2546/48 are3.3Vhigh-speed4,718,592-bit(4.5Mega-

bit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbuscycles

when turning the bus around between reads and writes, or writes and

reads. Thus, they have been given the name ZBT^TM, or Zero Bus

Turnaround.

PinDescriptionSummary

0-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE1, CE

, CE

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

, BW

CLK

ADV/LD

LBO

TMS

TDI

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

Synchronous

N/A

TCK

TDO

TRST

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

Static

JTAG Reset (Optional)

Sleep Mode

I/O

-I/O31, I/OP1-I/OP4

Data Input / Output

Core Power, I/O Power

Ground

DD, VDDQ

Supply

Static

5294 tbl 01

FEBRUARY 2007

DSC-5294/05

12 3 4 5 6 7...28

中文翻译

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与IDT71V2546S150B相关器件

型号	品牌	获取价格	描述	数据表
IDT71V2546S150BG	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2546S150BG8	IDT	获取价格	ZBT SRAM, 128KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119
IDT71V2546S150BGI	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2546S150BQ	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2546S150BQI	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2546S150PF	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2546S150PF8	IDT	获取价格	ZBT SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQ
IDT71V2546S150PFG	IDT	获取价格	暂无描述
IDT71V2546S150PFG8	IDT	获取价格	ZBT SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQFP-
IDT71V2546S150PFI	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

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