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IDT71V016SA12YI PDF预览

IDT71V016SA12YI

更新时间: 2024-02-21 21:24:34
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
9页 289K
描述
Standard SRAM, 64KX16, 12ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44

IDT71V016SA12YI 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOJ包装说明:0.400 INCH, PLASTIC, SOJ-44
针数:44Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.41Is Samacsys:N
最长访问时间:12 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-J44JESD-609代码:e0
长度:28.575 mm内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:44字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ44,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified座面最大高度:3.683 mm
最大待机电流:0.01 A最小待机电流:3.15 V
子类别:SRAMs最大压摆率:0.16 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:10.16 mm
Base Number Matches:1

IDT71V016SA12YI 数据手册

 浏览型号IDT71V016SA12YI的Datasheet PDF文件第3页浏览型号IDT71V016SA12YI的Datasheet PDF文件第4页浏览型号IDT71V016SA12YI的Datasheet PDF文件第5页浏览型号IDT71V016SA12YI的Datasheet PDF文件第7页浏览型号IDT71V016SA12YI的Datasheet PDF文件第8页浏览型号IDT71V016SA12YI的Datasheet PDF文件第9页 
IDT71V016SA, 3.3V CMOS Static RAM  
1 Meg (64K x 16-Bit)  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Read Cycle No. 2(1)  
tRC  
ADDRESS  
OE  
tAA  
tOH  
(3)  
t
OHZ  
(3)  
tOE  
(3)  
t
OLZ  
CS  
(2)  
t
ACS  
(3)  
tCHZ  
tCLZ  
BLE  
BHE,  
(2)  
(3)  
t
BE  
(3)  
tBHZ  
t
BLZ  
DATAOUT  
DATA OUTVALID  
3834 drw 07  
NOTES:  
1. WE is HIGH for Read Cycle.  
2. Addressmustbevalidpriortoorcoincidentwiththelaterof CS, BHE, orBLE transitionLOW;otherwisetAA isthelimitingparameter.  
3. Transitionismeasured±200mVfromsteadystate.  
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)  
tWC  
ADDRESS  
tAW  
CS  
(2)  
(5)  
(5)  
tCW  
tCHZ  
tBHZ  
tBW  
BHE BLE  
,
tWR  
tWP  
WE  
tAS  
(5)  
tWHZ  
(5)  
tOW  
tDH  
(3)  
DATAOUT  
DATAIN  
PREVIOUS DATA VALID  
DATA VALID  
tDW  
DATAIN VALID  
3834 drw 08  
NOTES:  
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.  
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed  
on the bus for the required tDW. If OE is HIGH during a WEcontrolled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.  
3. Duringthisperiod, I/Opinsareintheoutputstate, andinputsignalsmustnotbeapplied.  
4. IftheCSLOWorBHEandBLELOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahigh-impedancestate.  
5. Transitionismeasured±200mVfromsteadystate.  
6.462  

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