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IDT71T75902S75BG PDF预览

IDT71T75902S75BG

更新时间: 2024-01-12 02:00:53
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
26页 386K
描述
ZBT SRAM, 1MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

IDT71T75902S75BG 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:BGA
包装说明:BGA, BGA119,7X17,50针数:119
Reach Compliance Code:not_compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.25
最长访问时间:7.5 ns其他特性:FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK):100 MHzI/O 类型:COMMON
JESD-30 代码:R-PBGA-B119JESD-609代码:e0
长度:22 mm内存密度:18874368 bit
内存集成电路类型:ZBT SRAM内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:119字数:1048576 words
字数代码:1000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1MX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:2.5 V
认证状态:Not Qualified座面最大高度:2.36 mm
最大待机电流:0.04 A最小待机电流:2.38 V
子类别:SRAMs最大压摆率:0.275 mA
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT71T75902S75BG 数据手册

 浏览型号IDT71T75902S75BG的Datasheet PDF文件第2页浏览型号IDT71T75902S75BG的Datasheet PDF文件第3页浏览型号IDT71T75902S75BG的Datasheet PDF文件第4页浏览型号IDT71T75902S75BG的Datasheet PDF文件第5页浏览型号IDT71T75902S75BG的Datasheet PDF文件第6页浏览型号IDT71T75902S75BG的Datasheet PDF文件第7页 
512K x 36, 1M x 18  
2.5V Synchronous ZBT™ SRAMs  
2.5V I/O, Burst Counter  
Flow-Through Outputs  
IDT71T75702  
IDT71T75902  
Features  
The IDT71T75702/902 contain address, data-in and control signal  
registers.Theoutputsareflow-through(nooutputdataregister).Output  
enable is the only asynchronous signal and can be used to disable the  
outputsatanygiventime.  
AClockEnable(CEN)pinallowsoperationoftheIDT71T75702/902  
to be suspended as long as necessary. All synchronous inputs are  
ignoredwhenCENishighandtheinternaldeviceregisterswillholdtheir  
previous values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite  
isinitiated.  
The IDT71T75702/902 have an on-chip burst counter. In the burst  
mode,theIDT71T75702/902canprovidefourcyclesofdataforasingle  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter  
(ADV/LD = HIGH).  
512K x 36, 1M x 18 memory configurations  
Supports high performance system speed - 100 MHz  
(7.5 ns Clock-to-Data Access)  
ZBT Feature - No dead cycles between write and read cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
2.5V power supply (±5%)  
2.5V (±5%) I/O Supply (VDDQ)  
Power down controlled by ZZ input  
TM  
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA)  
Description  
The IDT71T75702/902 are 2.5V high-speed 18,874,368-bit  
(18 Megabit) synchronous SRAMs organized as 512K x 36 /1M x 18.  
They are designed to eliminate dead bus cycles when turning the bus  
aroundbetweenreadsandwrites,orwritesandreads.Thustheyhave  
The IDT71T75702/902 SRAMs utilize IDT’s high-performance  
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm  
100-pinplasticthinquadflatpack(TQFP)aswellasa119 ballgridarray  
(BGA).  
TM  
been given the name ZBT , or Zero Bus Turnaround.  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andonthenextclockcycletheassociateddatacycleoccurs,be  
it read or write.  
PinDescriptionSummary  
A0-A19  
Ad d re ss Inp uts  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/ O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1, CE2, CE2  
OE  
Output Enable  
W
R/  
CEN  
BW1 BW2 BW3 BW4  
Read/Write Signal  
Clock Enable  
Individual Byte Write Selects  
Clock  
,
,
,
CLK  
ADV/LD  
Advance Burst Address/Load New Address  
Linear/Interleaved Burst Order  
Tes t Mo de S el e ct  
Test Data Input  
Synchronous  
Static  
LBO  
TMS  
TDI  
N/A  
N/A  
TCK  
TDO  
Te s t C loc k  
N/A  
Te s t D ata Outp ut  
JTAG Reset (Optional)  
Sleep Mode  
N/A  
Asynchronous  
Synchronous  
Synchronous  
Static  
TRST  
ZZ  
I/ O0-I/O31, I/OP1-I/OP4  
VDD, VDDQ  
Data Input/Output  
Co re Po wer, I/O Power  
Ground  
Supply  
Supply  
VSS  
Static  
5319 tbl 01  
FEBRUARY 2009  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC-5319/08  

IDT71T75902S75BG 替代型号

型号 品牌 替代类型 描述 数据表
71T75902S75BGG IDT

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2.5V Synchronous ZBT SRAM 2.5V I/O, Burst Counter Flow-Through Outputs
71T75902S75BG8 IDT

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2.5V Synchronous ZBT SRAM 2.5V I/O, Burst Counter Flow-Through Outputs

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IDT71T75902S75BGG IDT

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