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IDT71256S35Y PDF预览

IDT71256S35Y

更新时间: 2024-11-22 22:57:19
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
9页 82K
描述
CMOS STATIC RAM 256K (32K x 8-BIT)

IDT71256S35Y 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOJ包装说明:0.300 INCH, SOJ-28
针数:28Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.67最长访问时间:35 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-J28
JESD-609代码:e0长度:17.9324 mm
内存密度:262144 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端口数量:1
端子数量:28字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX8输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装等效代码:SOJ28,.34
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified座面最大高度:3.556 mm
最大待机电流:0.015 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.155 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
宽度:7.5184 mmBase Number Matches:1

IDT71256S35Y 数据手册

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IDT71256S  
IDT71256L  
CMOS STATIC RAM  
256K (32K x 8-BIT)  
Integrated Device Technology, Inc.  
FEATURES:  
• High-speed address/chip select time  
DESCRIPTION:  
— Military: 25/30/35/45/55/70/85/100/120/150ns (max.)  
— Commercial: 20/25/35/45ns (max.) Low Power only.  
• Low-power operation  
The IDT71256 is a 262,144-bit high-speed static RAM  
organized as 32K x 8. It is fabricated using IDT’s high-  
performance, high-reliability CMOS technology.  
• Battery Backup operation — 2V data retention  
• Produced with advanced high-performance CMOS  
technology  
• Input and output directly TTL-compatible  
• Available in standard 28-pin (300 or 600 mil) ceramic  
DIP, 28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ  
and 32-pin LCC  
Address access times as fast as 20ns are available with  
power consumption of only 350mW (typ.). The circuit also  
offers a reduced power standby mode. When CSgoes HIGH,  
the circuit will automatically go to, and remain in, a low-power  
standbymodeaslongasCSremainsHIGH. Inthefullstandby  
mode, the low-power device consumes less than 15µW,  
typically. This capability provides significant system level  
power and cooling savings. The low-power (L) version also  
offers a battery backup data retention capability where the  
circuit typically consumes only 5µW when operating off a 2V  
battery.  
• Military product compliant to MIL-STD-883, Class B  
The lDT71256 is packaged in a 28-pin (300 or 600 mil)  
ceramic DIP, a 28-pin 300 mil J-bend SOlC, and a 28-pin (600  
mil) plastic DIP, and 32-pin LCC providing high board-level  
packing densities.  
TheIDT71256militaryRAMismanufacturedincompliance  
with the latest revision of MIL-STD-883, Class B, making it  
ideally suited to military temperature applications demanding  
the highest level of performance and reliability.  
FUNCTIONAL BLOCK DIAGRAM  
A0  
VCC  
GND  
262,144 BIT  
MEMORY ARRAY  
ADDRESS  
DECODER  
A14  
I/O 0  
I/O CONTROL  
INPUT  
DATA  
CIRCUIT  
I/O 7  
CS  
CONTROL  
CIRCUIT  
WE  
OE  
2946 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AUGUST 1996  
1996 Integrated Device Technology, Inc.  
DSC-2946/7  
7.2  
1

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