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IDT70V7589S PDF预览

IDT70V7589S

更新时间: 2024-10-28 23:01:07
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
22页 495K
描述
HIGH-SPEED 3.3V 64K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

IDT70V7589S 数据手册

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HIGH-SPEED 3.3V 64K x 36  
SYNCHRONOUS  
BANK-SWITCHABLE  
IDT70V7589S  
DUAL-PORT STATIC RAM  
WITH 3.3V OR 2.5V INTERFACE  
Features:  
– 1.5ns setup to clock and 0.5ns hold on all control, data, and  
address inputs @ 200MHz  
Data input, address, byte enable and control registers  
– Self-timedwriteallowsfastcycletime  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
LVTTL- compatible, 3.3V (±150mV) power supply  
for core  
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V  
(±100mV) power supply for I/Os and control signals on  
each port  
Industrial temperature range (-40°C to +85°C) is  
available at 166MHz and 133MHz  
Available in a 208-pin Plastic Quad Flatpack (PQFP),  
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball  
GridArray(BGA)  
64K x 36 Synchronous Bank-Switchable Dual-ported SRAM  
Architecture  
64 independent 1K x 36 banks  
– 2 megabits of memory on chip  
Bank access controlled via bank address pins  
High-speed data access  
– Commercial:3.4ns (200MHz)/3.6ns (166MHz)/  
4.2ns (133MHz) (max.)  
Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)  
Selectable Pipelined or Flow-Through output mode  
Counter enable and repeat features  
Dual chip enables allow for depth expansion without  
additional logic  
Full synchronous operation on both ports  
– 5ns cycle time, 200MHzoperation(14Gbps bandwidth)  
– Fast 3.4ns clock to data out  
Supports JTAG features compliant with IEEE 1149.1  
FunctionalBlockDiagram  
PL/FTL  
OPTL  
PL/FTR  
OPTR  
CLKL  
CLKR  
ADSL  
ADSR  
CNTENL  
REPEATL  
R/WL  
CNTENR  
REPEATR  
R/WR  
CE0R  
CE1R  
MUX  
CE0L  
CE1L  
BE3L  
BE2L  
BE1L  
BE0L  
OEL  
CONTROL  
LOGIC  
CONTROL  
LOGIC  
1Kx36  
MEMORY  
ARRAY  
BE3R  
BE2R  
BE1R  
BE0R  
OER  
(BANK 0)  
MUX  
MUX  
I/O  
CONTROL  
I/O  
CONTROL  
I/O0L-35L  
I/O0R-35R  
1Kx36  
MEMORY  
ARRAY  
A9R  
A0R  
(BANK 1)  
A9L  
A0L  
ADDRESS  
DECODE  
ADDRESS  
DECODE  
MUX  
BA5R  
BA4R  
BA3R  
BA2R  
BA1R  
BA0R  
BA5L  
BA4L  
3L  
BANK  
DECODE  
BA  
BA  
BANK  
DECODE  
2L  
BA1L  
BA0L  
MUX  
1Kx36  
MEMORY  
ARRAY  
(BANK 63)  
NOTE:  
MUX  
1. The Bank-Switchable dual-port uses a true SRAM  
core instead of the traditional dual-port SRAM core.  
As a result, it has unique operating characteristics.  
Please refer to the functional description on page 19  
for details.  
,
5627 drw 01  
TMS  
TCK  
TRST  
TDI  
TDO  
JTAG  
DECEMBER 2002  
1
DSC 5627/4  
©2002IntegratedDeviceTechnology,Inc.  

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