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IDT70V05S20G PDF预览

IDT70V05S20G

更新时间: 2024-11-22 23:01:07
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
22页 173K
描述
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

IDT70V05S20G 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:PGA
包装说明:PGA, PGA68,11X11针数:68
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.26
最长访问时间:20 nsI/O 类型:COMMON
JESD-30 代码:S-CPGA-P68JESD-609代码:e0
长度:29.464 mm内存密度:65536 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
功能数量:1端口数量:2
端子数量:68字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX8输出特性:3-STATE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装等效代码:PGA68,11X11封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified座面最大高度:5.207 mm
最大待机电流:0.005 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.2 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
处于峰值回流温度下的最长时间:30宽度:29.464 mm

IDT70V05S20G 数据手册

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IDT70V05S/L  
HIGH-SPEED 3.3V  
8K x 8 DUAL-PORT  
STATIC RAM  
Features  
using the Master/Slave select when cascading more than  
one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
TTL-compatible, single 3.3V (±0.3V) power supply  
Available in 68-pin PGA and PLCC, and a 64-pin TQFP  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
Commercial: 15/20/25/35/55ns (max.)  
Industrial:20/25/35/55ns(max.)  
Low-power operation  
IDT70V05S  
Active:400mW(typ.)  
Standby: 3.3mW (typ.)  
IDT70V05L  
Active:380mW(typ.)  
Standby: 660µW (typ.)  
IDT70V05 easily expands data bus width to 16 bits or more  
Functional Block Diagram  
OER  
CER  
OEL  
CEL  
R/W  
R/W  
R
L
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
(1,2)  
(1,2)  
BUSYL  
BUSYR  
A12L  
A0L  
A12R  
A0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CEL  
OEL  
CER  
OER  
R/WR  
R/WL  
SEM  
INTL  
L
SEM  
INTR  
R
M/S  
(2)  
(2)  
2941 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
MARCH 2000  
1
DSC 2941/6  
©2000IntegratedDeviceTechnology,Inc.  

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