IDT70T651S10DRI

更新时间： 2024-10-28 22:34:11

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
27页	343K
描述
HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE

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中文翻译

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数据手册

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IDT70T651S10DRI 数据手册

HIGH-SPEED 2.5V

PRELIMINARY

IDT70T651/9S

256/128K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

◆

Busy and Interrupt Flags

On-chip port arbitration logic

Features

◆

True Dual-Port memory cells which allow simultaneous

◆

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

access of the same memory location

High-speed access

◆

– Commercial:8/10/12/15ns(max.)

– Industrial: 10/12ns(max.)

◆

RapidWrite Mode simplifies high-speed consecutive write

◆

Sleep Mode Inputs on both ports

cycles

◆

Supports JTAG features compliant to IEEE 1149.1

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad

Flatpack and 208-ball fine pitch Ball Grid Array.

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Dual chip enables allow for depth expansion without

external logic

◆

IDT70T651/9 easily expands data bus width to 72 bits or

more using the Master/Slave select when cascading more

than one device

◆

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Functional Block Diagram

BE3L

BE3R

BE2R

BE2L

BE1L

BE0L

BE1R

BE0R

R/WL

R/WR

B B B B

E E E E

B B B

E E E

2 1 0

CE0L

CE1L

CE0R

CE1R

R R R R

OEL

OER

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

256/128K x 36

MEMORY

ARRAY

I/O0L- I/O35L

Di n_L

Di n_R

I/O0R -I/O35R

(1)

17R

(1)

17L

Address

Decoder

Address

Decoder

ADDR_L

ADDR_R

A0L

CE0L

CE1L

ARBITRATION

CE0R

CE1R

TDI

TC K

TMS

TRST

JTAG

INTERRUPT

SEMAPHORE

LOGIC

TD O

R/WL

R/W

(2,3)

(3)

(2,3)

BUSY

SEM

M/S

SEM

(3)

INT

(4)

ZZR

ZZL

CONTROL

LOGIC

NOTES:

1. Address A17x is a NC for IDT70T659.

2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

4869 drw 01

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep

mode pins themselves (ZZx) are not affected during sleep mode.

NOVEMBER 2003

DSC-5632/3

12 3 4 5 6 7...27

中文翻译

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与IDT70T651S10DRI相关器件

型号	品牌	获取价格	描述	数据表
IDT70T651S12BC	IDT	获取价格	HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T651S12BC8	IDT	获取价格	Dual-Port SRAM, 256KX36, 12ns, CMOS, PBGA256, BGA-256
IDT70T651S12BCG8	IDT	获取价格	Dual-Port SRAM, 256KX36, 12ns, CMOS, PBGA256, BGA-256
IDT70T651S12BCGI	IDT	获取价格	Dual-Port SRAM, 256KX36, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM PITCH, GREEN, BGA-256
IDT70T651S12BCGI8	IDT	获取价格	Dual-Port SRAM, 256KX36, 12ns, CMOS, PBGA256, BGA-256
IDT70T651S12BCI	IDT	获取价格	HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T651S12BF	IDT	获取价格	HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T651S12BFG8	IDT	获取价格	Dual-Port SRAM, 256KX36, 12ns, CMOS, PBGA208, FBGA-208
IDT70T651S12BFGI	IDT	获取价格	Dual-Port SRAM, 256KX36, 12ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM PITCH, GREEN, FBGA-208
IDT70T651S12BFGI8	IDT	获取价格	Dual-Port SRAM, 256KX36, 12ns, CMOS, PBGA208, FBGA-208

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