Datasheet > 存储 > SRAM> IDT70T3799MS166BBGI

IDT70T3799MS166BBGI

更新时间： 2024-10-29 03:15:11

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
25页	304K
描述
HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

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中文翻译

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数据手册

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HIGH-SPEED 2.5V

ADVANCED

IDT70T3719/99M

256/128K x 72

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– 1.7ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 166MHz

– Data input, address, byte enable and control registers

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

◆

– Commercial:3.6ns (166MHz)/

4.2ns (133MHz)(max.)

◆

– Industrial: 4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Interrupt and Collision Detection Flags

Full synchronous operation on both ports

– 6ns cycletime,166MHzoperation(23.9Gbps bandwidth)

– Fast 3.6ns clock to data out

◆

Industrial temperature range (-40°C to +85°C) is

available at 133MHz

◆

Available in a 324-pin Green Ball Grid Array (BGA)

Includes JTAG Functionality

– Self-timedwriteallowsfastcycletime

FunctionalBlockDiagram

BE7R

BE7L

BE0L

BE0R

FT/PIPE

0a 1a

0h 1h

1h 0h

1a 0a

FT/PIPER

1/0

R/WL

R/WR

CE0L

CE0R

CE1R

CE1L

1/0

OUT0-8_L

OUT9-17_L

OUT0-8_R

OUT9-17_R

OUT18-26_L

OUT27-35_L

OUT36-44_L

OUT45-53_L

OUT54-62_L

OUT63-72_L

OUT18-26_R

OUT27-35_R

OUT36-44_R

OUT45-53_R

OUT54-62_R

OUT63-72_R

1h 0h

1a 0a

0a 1a

0h 1h

0/1

FT/PIPE

256/128K x 72

MEMORY

ARRAY

Byte 7

Byte 0

I/O0R - I/O71R

Byte 0

I/O0L - I/O71L

Byte 7

IN_L

IN_R

CLK

CLKR

(1)

17L

(1)

17R

REPEAT

ADS

Counter/

Address

Reg.

Counter/

Address

Reg.

ADDR_R

ADDR_L

REPEAT

ADS

CNTEN

INTERRUPT

TDI

TDO

TCK

TMS

TRST

COLLISION

DETECTION

LOGIC

JTAG

R/W

COL

INT

INT_L

(2)

ZZR

CONTROL

LOGIC

5687 drw 01

NOTES:

1. Address A17 is a NC for the IDT70T3799.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx

JUNE 2005

and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

DSC 5687/1

12 3 4 5 6 7...25

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与IDT70T3799MS166BBGI相关器件

型号	品牌	获取价格	描述	数据表
IDT70T631S	IDT	获取价格	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T631S10BC	IDT	获取价格	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T631S10BC8	IDT	获取价格	Dual-Port SRAM, 256KX18, 10ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-
IDT70T631S10BCG	IDT	获取价格	Dual-Port SRAM, 256KX18, 10ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HIEGHT, 1 MM PITCH, GREE
IDT70T631S10BCG8	IDT	获取价格	Multi-Port SRAM, 256KX18, 10ns, CMOS, PBGA256
IDT70T631S10BCGI8	IDT	获取价格	Multi-Port SRAM, 256KX18, 10ns, CMOS, PBGA256
IDT70T631S10BCI	IDT	获取价格	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T631S10BCI8	IDT	获取价格	Dual-Port SRAM, 256KX18, 10ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-
IDT70T631S10BF	IDT	获取价格	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFAC
IDT70T631S10BF8	IDT	获取价格	Dual-Port SRAM, 256KX18, 10ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, F

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