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IDT709079S15PFI PDF预览

IDT709079S15PFI

更新时间: 2024-11-11 03:08:15
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
17页 306K
描述
HIGH-SPEED 32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM

IDT709079S15PFI 技术参数

生命周期:Obsolete包装说明:QFP,
Reach Compliance Code:compliant风险等级:5.44
最长访问时间:15 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码:S-PQFP-G100内存密度:262144 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
功能数量:1端子数量:100
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX8
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子位置:QUAD

IDT709079S15PFI 数据手册

 浏览型号IDT709079S15PFI的Datasheet PDF文件第2页浏览型号IDT709079S15PFI的Datasheet PDF文件第3页浏览型号IDT709079S15PFI的Datasheet PDF文件第4页浏览型号IDT709079S15PFI的Datasheet PDF文件第5页浏览型号IDT709079S15PFI的Datasheet PDF文件第6页浏览型号IDT709079S15PFI的Datasheet PDF文件第7页 
PRELIMINARY  
IDT709079S/L  
HIGH-SPEED 32K x 8  
SYNCHRONOUS  
DUAL-PORT STATIC RAM  
Features:  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:9/12/15ns(max.)  
– Industrial: 12ns (max.)  
Dual chip enables allow for depth expansion without  
additional logic  
Full synchronous operation on both ports  
– 4ns setup to clock and 1ns hold on all control, data,  
and address inputs  
Low-power operation  
– Data input, address, and control registers  
– IDT709079S  
Fast 9ns clock to data out in the Pipelined output mode  
Active:950mW(typ.)  
Standby: 5mW (typ.)  
– IDT709079L  
Active:950mW(typ.)  
Standby: 1mW (typ.)  
Flow-Through or Pipelined output mode on either port via  
the FT/PIPER pin  
Counter enable and reset features  
– Self-timedwriteallowsfastcycletime  
– 15ns cycle time, 66MHz operation in the Pipelined  
output mode  
TTL- compatible, single 5V (±10%) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Available in a 100 pin Thin Quad Flatpack (TQFP)  
FunctionalBlockDiagram  
R/W  
R
R
R/W  
L
OE  
OEL  
CE0R  
CE1R  
CE0L  
CE1L  
1
0
1
0
0/1  
0/1  
0
1
1
0
0/1  
0/1  
FT/PIPE  
L
FT/PIPE  
R
I/O0L - I/O7L  
I/O0R - I/O7R  
I/O  
Control  
I/O  
Control  
A
14R  
0R  
A
14L  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A
CLK  
ADS  
CNTEN  
CNTRST  
A
0L  
L
R
R
CLK  
ADS  
CNTEN  
CNTRST  
L
R
L
R
L
3495 drw 01  
DECEMBER 2002  
1
DSC 3495/8  
©2002IntegratedDeviceTechnology,Inc.  

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