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IDT7054L25G PDF预览

IDT7054L25G

更新时间: 2024-11-28 22:36:43
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
11页 100K
描述
HIGH-SPEED 4K x 8 FourPort STATIC RAM

IDT7054L25G 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:PGA
包装说明:CERAMIC, PGA-108针数:108
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.82
最长访问时间:25 ns其他特性:AUTOMATIC POWER DOWN; LOW POWER STANDBY MODE
I/O 类型:COMMONJESD-30 代码:S-CPGA-P108
JESD-609代码:e0长度:30.48 mm
内存密度:32768 bit内存集成电路类型:FOUR-PORT SRAM
内存宽度:8功能数量:1
端口数量:4端子数量:108
字数:4096 words字数代码:4000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4KX8
输出特性:3-STATE可输出:YES
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装等效代码:PGA108,12X12封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:5.207 mm
最大待机电流:0.0015 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.305 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
处于峰值回流温度下的最长时间:30宽度:30.48 mm
Base Number Matches:1

IDT7054L25G 数据手册

 浏览型号IDT7054L25G的Datasheet PDF文件第2页浏览型号IDT7054L25G的Datasheet PDF文件第3页浏览型号IDT7054L25G的Datasheet PDF文件第4页浏览型号IDT7054L25G的Datasheet PDF文件第5页浏览型号IDT7054L25G的Datasheet PDF文件第6页浏览型号IDT7054L25G的Datasheet PDF文件第7页 
IDT7054S/L  
HIGH-SPEED  
4K x 8 FourPortTM  
STATIC RAM  
TTL-compatible; single 5V (±10%) power supply  
Available in 128 pin Thin Quad Flatpack and 108 pin PGA  
packages  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
ꢀeatures  
High-speed access  
– Commercial:20/25/35ns (max.)  
Industrial:25ns (max.)  
Military:25/35ns(max.)  
Low-power operation  
Description  
IDT7054S  
Active:750mW(typ.)  
Standby: 7.5mW (typ.)  
IDT7054L  
Active:750mW(typ.)  
Standby: 1.5mW (typ.)  
True FourPort memory cells which allow simultaneous  
TheIDT7054isahigh-speed4Kx8FourPort™StaticRAMdesigned  
to be used in systems where multiple access into a common RAM is  
required.ThisFourPortStaticRAMoffersincreasedsystemperformance  
inmultiprocessorsystemsthathaveaneedtocommunicateinrealtimeand  
alsooffersaddedbenefitforhigh-speedsystemsinwhichmultipleaccess  
is requiredinthe same cycle.  
access of the same memory locations  
Fully asynchronous operation from each of the four ports:  
P1, P2, P3, and P4  
TheIDT7054is alsodesignedtobeusedinsystems whereon-chip  
hardware port arbitration is not needed. This part lends itself to those  
systems whichcannottoleratewaitstates oraredesignedtobeableto  
ꢀunctionalBlockDiagram  
R/WP1  
CEP1  
R/WP4  
CEP4  
OEP1  
OEP4  
COLUMN  
I/O  
COLUMN  
I/O0P1-I/O7P1  
I/O0P4-I/O7P4  
I/O  
PORT 1  
PORT 4  
ADDRESS  
DECODE  
LOGIC  
ADDRESS  
DECODE  
LOGIC  
A0P1 - A11P1  
A0P2 - A11P2  
A0P4 - A11P4  
MEMORY  
ARRAY  
PORT 2  
ADDRESS  
DECODE  
LOGIC  
PORT 3  
ADDRESS  
DECODE  
LOGIC  
A0P3 - A11P3  
COLUMN  
I/O  
COLUMN  
I/O  
I/O0P2-I/O7P2  
I/O0P3-I/O7P3  
OEP2  
OEP3  
CEP2  
CEP3  
R/WP3  
R/WP2  
3241 drw 01  
NOVEMBER 2001  
1
DSC 3241/11  
©2001IntegratedDeviceTechnology,Inc.  

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