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IDT54FCT88915TT70

更新时间： 2024-11-07 22:19:03

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器
页数	文件大小	规格书
11页	144K
描述
LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

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IDT54/74FCT88915TT 55/70/100/133

LOW SKEW PLL-BASED CLOCK DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT54/74FCT88915TT

55/70/100/133

LOW SKEW PLL-BASED

CMOS CLOCK DRIVER

(WITH 3-STATE)

PRELIMINARY

Integrated Device Technology, Inc.

is fed back to the PLL at the FEEDBACK input resulting in

essentially delay across the device. The PLL consists of the

phase/frequency detector, charge pump, loop filter and VCO.

The VCO is designed for a 2Q operating frequency range of

40MHz to f2Q Max.

The IDT54/74FCT88915TT provides 8 outputs with 500ps

skew. The Q5 output is inverted from the Q outputs. The 2Q

runs at twice the Q frequency and Q/2 runs at half the Q

frequency.

FEATURES:

• 0.5 MICRON CMOS Technology

• Input frequency range: 10MHz – f2Q Max. spec

(FREQ_SEL = HIGH)

• Max. output frequency: 133MHz

• Pin and function compatible with MC88915T

• 5 non-inverting outputs, one inverting output, one 2x

output, one ÷2 output; all outputs are TTL-compatible

• 3-State outputs

TheFREQ_SELcontrolprovidesanadditional÷ 2optionin

the output path. PLL _EN allows bypassing of the PLL, which

is useful in static test modes. When PLL_EN is low, SYNC

input may be used as a test clock. In this test mode, the input

frequency is not limited to the specified range and the polarity

of outputs is complementary to that in normal operation

(PLL_EN = 1). The LOCK output attains logic HIGH when the

PLL is in steady-state phase and frequency lock. When OE/

• Output skew < 500ps (max.)

• Duty cycle distortion < 500ps (max.)

• Part-to-part skew: 1ns (from tPD max. spec)

• TTL level output voltage swing

• 64/–15mA drive at TTL output voltage levels

• Available in 28 pin PLCC, LCC and SSOP packages

DESCRIPTION:

The IDT54/74FCT88915TT uses phase-lock loop technol- RST is low, all the outputs are put in high impedance state and

ogy to lock the frequency and phase of outputs to the input registers at Q, Q and Q/2 outputs are reset.

reference clock. It provides low skew clock distribution for

The IDT54/74FCT88915TT requires one external loop

high performance PCs and workstations. One of the outputs filter component as recommended in Figure 1.

FUNCTIONAL BLOCK DIAGRAM

FEEDBACK

LOCK

Voltage

Controlled

Oscilator

Phase/Freq.

Detector

SYNC (0)

SYNC (1)

Charge Pump

REF_SEL

PLL_EN

Mux

(÷1)

(÷2)

Divide

-By-2

FREQ_SEL

OE/RST

Q/2

3072 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AUGUST 1995

1995 Integrated Device Technology, Inc.

9.7

DSC-4247/1

12 3 4 5 6 7...11

中文翻译

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与IDT54FCT88915TT70相关器件

型号	品牌	获取价格	描述	数据表
IDT54FCT88915TT70J	IDT	获取价格	LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
IDT54FCT88915TT70JB	IDT	获取价格	LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
IDT54FCT88915TT70L	IDT	获取价格	LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
IDT54FCT88915TT70LB	IDT	获取价格	LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
IDT54FCT88915TT70PY	IDT	获取价格	LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
IDT54FCT88915TT70PYB	IDT	获取价格	LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
IDT54HCT139LB-1	IDT	获取价格	Decoder/Driver, CMOS, CQCC20
IDT54LVC162374APA	IDT	获取价格	3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O
IDT54LVC162374APF	IDT	获取价格	3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O
IDT54LVC162374APV	IDT	获取价格	3.3V CMOS 16-BIT EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O

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